US4135102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High performance inverter circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1977-07-18
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Granted: 1979-01-16
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Expires: 1997-07-18
Abstract
Abstract The invention disclosed herein is a high performance inverter circuit using MOSFETs having varying threshold voltages produced by selectively varying ion implantation doses in the channels of the MOSFETs and using a slightly depletion type MOSFET, rather than a conventional depletion type, in the output stage.
Inventors
- 👤 Robert S. Green
- 👤 Harold W. Dozier
- 👤 Vernon G. McKenny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:48
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H03K19/09445
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
155 words
An integrated circuit for inverting a binary logic signal comprising: a first depletion mode FET coupling a drain voltage to a first output node, the gate of the first depletion mode FET being connected to the first output node, a first enhancement mode FET coupling the first output node to a source voltage, the gate of the first enhancement mode FET being connected to an input terminal, a second depletion mode FET coupling a drain voltage to a second output node, the gate of the second depletion mode FET being connected to the first output node, and a second enhancement mode FET coupling the second output node to a source voltage, the gate of the second enhancement mode FET being connected to the input terminal, wherein the absolute value of the threshold voltage of the second depletion mode FET is less than the absolute value of the threshold voltage of the first depletion mode FET.
Claim 2
Dependent Claim
155 words
An integrated circuit for inverting a binary logic signal comprising: a first depletion mode FET coupling a drain voltage to a first output node, the gate of the first depletion mode FET being connected to the first output node, a first enhancement mode FET coupling the first output node to a source voltage, the gate of the first enhancement mode FET being connected to an input terminal, a second depletion mode FET coupling a drain voltage to a second output node, the gate of the second depletion mode FET being connected to the first output node, and a second enhancement mode FET coupling the second output node to a source voltage, the gate of the second enhancement mode FET being connected to the input terminal, wherein the absolute value of the threshold voltage of the second depletion mode FET is less than the absolute value of the threshold voltage of the first depletion mode FET.
Claim 3
Dependent Claim
62 words
The integrated circuit of claim 1 wherein the absolute value of the threshold voltage of the second depletion mode FET is substantially less than the difference between the high and low logic levels, whereby the second depletion mode FET will be pinched-off during most of the transition from the high logic level to the low logic level of the second output node.
References Cited (Backward Citations)
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US3775693A
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US3851189A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-15 | 1982-07-17 | 1983-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-15 | 1986-07-17 | 1987-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-15 | 1990-07-17 | 1991-01-16 | $7700.00 | Window Closed / Lapsed |