Information refreshing system in a semiconductor memory

Claim 1

In a data processing system comprising a central processor interactive with a plurality of peripheral units and a main working semiconductor memory by means of interrupt requests sent by said peripheral units and by said working memory to said central processor, said interrupt requests having relative priority with respect to each other, said semiconductor memory including a plurality of memory cells arranged in a plurality of rows each row of which must be refreshed within a predetermined time interval after the last preceding refreshing operation; a refresh control system comprising: refresh control means, including addressing means, responsive to a refresh command received from said central processor to sequentially refresh said rows of memory cells, one row at each receipt of said refresh command, timing means for generating a sequence of pulses having a preestablished repetition rate, first circuit means responsive to said timing means for generating an interrupt request signal of low relative priority in synchronism with said repetition rate, said first circuit means including means for extinguishing said interrupt request signal upon the occurrence of a responsive refresh command, and second circuit means responsive to said timing means and to said first circuit means to generate an interrupt request signal of highest relative priority if a refresh command is not received by said first circuit means within a preestablished interval following the generation of an interrupt request signal of said low relative priority.