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US4125427A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of processing a semiconductor

Assignee: LSI Logic FSI Corp
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Filing: 1976-08-27
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Granted: 1978-11-14
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Expires: 1996-08-27
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Abstract

Abstract An improvement of the prior art method of processing large scale integrated (LSI) semiconductors is disclosed, wherein an etching procedure, which was previously performed as the final processing step, is now done at an earlier stage to preclude damage to the surface of the wafer on which the active devices are formed. In the prior art method of fabricating an active device on a semiconductor wafer, an undesirable layer of field oxide manifests itself on the reverse side when the field oxide is grown on the obverse or principal side of the wafer. The prior processing philosophy was to allow the oxide layer to remain on the wafer until after the processing was completed and, as a final step, the undesired oxide coating was removed. This was done by carefully placing the wafer in a pool of etchant so that only the reverse side is etched. Since the wafer is only about 12 mils thick, the operator had to exercise extreme caution in placing the wafer in the etchant to prevent the etchant from creeping up the thickness dimension of the wafer and thus etching the obverse side. Our novel method contemplates modifying the processing steps of the prior art by removing the undesired field oxide before the circuits or active devices have been completely formed, when the wafer may be completely immersed in the etchant without damaging or etching areas on the active portion of the wafer.

Inventors

  • 👤 Peter C. Chen
  • 👤 John K. Stewart, Jr.
  • 👤 Tuh-Kai Koo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 12:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10P; H10P14/00; H10P14/40; H10P14/416; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; Y; Y10; Y10S; Y10S438/00; Y10S438/928

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 157 words
In a method of processing a semiconductor device on the obverse side of a wafer wherein the device includes an electrode on the obverse side of the wafer, the improved process wherein an oxide layer formed on the reverse side of the wafer is removed prior to formation of the electrode and comprising: partially forming the device on the obverse side of a semiconductive wafer, including the step of growing a layer of oxide on selected portions of the obverse side of the wafer, the oxide being simultaneously undesirably grown on the reverse side of the wafer; providing a layer of etch resistant material on the layer of oxide on the obverse side of the wafer, the etch resistant material being suitable for forming a device electrode therefrom; selectively etching the oxide from the reverse side of the wafer prior to the formation of the electrode; and forming the layer of etch resistant material into an electrode.
Claim 2
Dependent Claim 157 words
In a method of processing a semiconductor device on the obverse side of a wafer wherein the device includes an electrode on the obverse side of the wafer, the improved process wherein an oxide layer formed on the reverse side of the wafer is removed prior to formation of the electrode and comprising: partially forming the device on the obverse side of a semiconductive wafer, including the step of growing a layer of oxide on selected portions of the obverse side of the wafer, the oxide being simultaneously undesirably grown on the reverse side of the wafer; providing a layer of etch resistant material on the layer of oxide on the obverse side of the wafer, the etch resistant material being suitable for forming a device electrode therefrom; selectively etching the oxide from the reverse side of the wafer prior to the formation of the electrode; and forming the layer of etch resistant material into an electrode.
Claim 3
Dependent Claim 60 words
The process of claim 1, wherein the step of growing the layer of oxide comprises: growing a first layer of field oxide on the selected portions of the obverse side of the wafer; and growing a layer of gate oxide over the entire obverse side of the wafer, the gate oxide simultaneously grown on the reverse side of the wafer.
Claim 4
Dependent Claim 28 words
The process of claim 2 wherein the etch resistant material is a layer of polysilicon and the polysilicon layer is formed to an electrode over the gate oxide.
Claim 5
Dependent Claim 62 words
The process of claim 1 wherein the oxide is removed solely from the reverse side of the wafer by immersing the entire wafer in an etchant comprising: (a) 7 parts NH 4 F and (b) 1 part HF; and wherein the etchant is at room temperature; and the wafer is maintained in the dilute etchant for a period of about 10-15 minutes.

References Cited (Backward Citations)

US3122817A Cited
US3811975A Cited
US3847690A Cited
US3852104A Cited
US3909325A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-11-13 1982-05-15 1982-11-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-11-13 1986-05-15 1986-11-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-11-13 1990-05-15 1990-11-14 $7700.00 Window Closed / Lapsed

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