Patent US4120744A successfully refreshed from Google Patents.
US4120744A
Expired / Lapsed
US
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Method of fabricating a thermal display device
Assignee: Texas Instruments Inc
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Filing: 1973-07-26
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Granted: 1978-10-17
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Expires: 1993-07-26
Abstract
Abstract A plurality of silicon elements are arranged in a printing array with the major faces co-planar and the edges interconnected into a monolithic structure by a grid of polycrystalline silicon and silicon dioxide. The silicon dioxide provides an electrical and thermal barrier, and the polycrystalline silicon provides a strong mechanical interconection. In the preferred embodiment, the silicon elements are monocrystalline and contain one or more electrical components for selectively heating the elements. The method for fabricating the device includes the steps of etching V-shaped grooves in one surface of a silicon slice and then successively growing silicon dioxide and polycrystalline silicon on the etched surface to form a thick slice. The other side of the slice is then lapped away to at least the depth of the silicon dioxide in the grooves and semiconductor elements and conductors formed in and/or on the lapped side. The lapped side is then bonded to a substrate and the polycrystalline silicon and silicon dioxide removed from the surfaces of the elements, but not from the grooves between the elements. The elements are thus part of a monolithic sheet having sufficient structural integrity to withstand thermal fracturing without producing print smearing from element to element.
Inventors
- 👤 Thomas R. Payne
- 👤 Harry K. James
- 👤 Millard M. Judy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:28
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1914; H10W10/021; H10W10/041; H10W10/20; H10W10/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
The method for fabricating a thermal display device which comprises: selectively etching one face of a slice of monocrystalline semiconductor material to form a grid of moats and an array of mesas, the tops of said mesas lying substantially in a plane, growing a relatively thick layer of oxide on the slice, the oxide layer being sufficiently thin to not fill the moats, depositing a layer of polycrystalline semiconductor material on the oxide layer on said one face to provide a thick monolithic structure for processing, then removing monocrystalline semiconductor material from the face opposite said one face of the slice to the depth of the oxide layer in the moats, then forming circuit components in said mesas for converting said mesas into heat dissipating devices, then forming electrical conductors on said opposite face for contacting said circuit components, then mounting said device on an insulated substrate, and then removing only the polycrystalline semiconductor material and the layer of oxide overlying said plane while leaving sufficient polycrystalline semiconductor material and oxide in the moats to interconnect the mesas into a monolithic structure.
Claim 2
Independent Claim
182 words
The method for fabricating a thermal display device which comprises: selectively etching one face of a slice of monocrystalline semiconductor material to form a grid of moats and an array of mesas, the tops of said mesas lying substantially in a plane, growing a relatively thick layer of oxide on the slice, the oxide layer being sufficiently thin to not fill the moats, depositing a layer of polycrystalline semiconductor material on the oxide layer on said one face to provide a thick monolithic structure for processing, then removing monocrystalline semiconductor material from the face opposite said one face of the slice to the depth of the oxide layer in the moats, then forming circuit components in said mesas for converting said mesas into heat dissipating devices, then forming electrical conductors on said opposite face for contacting said circuit components, then mounting said device on an insulated substrate, and then removing only the polycrystalline semiconductor material and the layer of oxide overlying said plane while leaving sufficient polycrystalline semiconductor material and oxide in the moats to interconnect the mesas into a monolithic structure.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein all semiconductor material is silicon and the oxide is silicon dioxide.
Claim 4
Dependent Claim
30 words
The method of claim 1 wherein said step of removing only the polycrystalline semiconductor material and the layer of oxide comprises lapping the polycrystalline semiconductor material and the oxide layer.
Claim 5
Dependent Claim
205 words
The method of claim 1 wherein said step of depositing comprises the steps of: depositing a first relatively thin layer of polycrystalline semiconductor material of a predetermined thickness overlying said thick oxide so as not to fill said moats, forming a relatively thin second layer of oxide overlying said first polycrystalline layer such that said relatively thick and relatively thin oxide layers in combination with said first polycrystalline layer do not fill said moats, depositing a second relatively thick layer of polycrystalline semiconductor material overlying said second oxide layer to provide a thick monolithic structure for processing, and wherein said step of removing only the polycrystalline semiconductor material and the layer of oxide comprises the steps of: (i) selectively etching with a first solution the polycrystalline semiconductor material overlying the second layer of oxide, (ii) selectively removing the second oxide layer only above said plane by using a second selective etch solution which preferentially attacks the oxide layer as compared to the underlying semiconductor material, (iii) selectively removing said first layer of polycrystalline semiconductor material only above said plane by selectively etching to said first oxide layer, and (iv) selectively removing said relatively thick oxide layer only above said plane by etching to said mesas.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-16 | 1982-04-17 | 1982-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-16 | 1986-04-17 | 1986-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-16 | 1990-04-17 | 1990-10-17 | $7700.00 | Window Closed / Lapsed |