US4110637A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic system for capacitively storing a signal voltage of predetermined level
Assignee: Ebauches SA
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Filing: 1977-07-12
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Granted: 1978-08-29
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Expires: 1997-07-12
Abstract
Abstract An electronic circuit arrangement designed to store for an indefinite period a signal voltage of predetermined magnitude briefly applied thereto, comprises a main storage capacitor C s connected via a first semiconductor switch T 1 across a supply of unipolar voltage and via a second semiconductor switch T 2 across an ancillary storage capacitor C x , the latter lying in series with a binary capacitor C i between two conductors M, Φ 1 across which a clock pulse V.sub.Φ1 is periodically generated. The semiconductor switches are field-effect transistors of the insulated-gate type (IGFETs), the gate of the first IGFET T 1 being tied to the junction X between the ancillary storage capacitor C x and the gate of the binary capacitor C i ; this junction X communicates with the junction S between the two IGFETs and the main storage capacitor C s in the conductive state of the second IGFET T 2 whose gate receives a series of unblocking pulses V.sub.Φ2, lagging behind the clock pulses V.sub.Φ1. The unblocking pulses may be generated at the same cadence as the train of clock pulses, in interleaved relationship therewith; they could also be derived from the junction S between the first IGFET T 1 and capacitor C s by having that junction tied to the gate of the second IGFET T 2 , the latter thus acting as a diode which conducts after the first IGFET T 1 has been turned on to recharge the capacitor C s . The generator of clock pulses V.sub.Φ1 may serve as the voltage supply for the first IGFET T 1 by having one of its conductors, Φ 1 , joined to the channel of that IGFET via a third IGFET T 3 connected as a diode.
Inventors
- 👤 Andreas Rusznyak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:53
CPC Classifications
G; G04; G04G; G04G99/00; G04G19/00; G04G99/003; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
338 words
A circuit arrangement for the storage of a signal voltage of predetermined level, comprising: two conductors connected across a source of recurrent unipolar clock pulses, one of said conductors being grounded; a main storage capacitor and an ancillary storage capacitor both connected to said one of said conductors; supply means including at least said one of said conductors for charging said main storage capacitor with a voltage having the same polarity as said clock pulses; a normally nonconductive first semiconductor element inserted between said supply means and said main storage capacitor on the side opposite said one of said conductors, said first semiconductor element forming a first junction with said main storage capacitor and being provided with a control electrode; a binary capacitor of the same conductivity type as said first semiconductor element inserted between said ancillary storage capacitor and the other of said conductors, said binary capacitor forming with said ancillary storage capacitor a second junction tied to said control electrode, at least one of said junctions being temporarily connectable to an external signaling circuit for the selective charging and discharging of the respective storage capacitor, the capacitance of said binary capacitor in the presence of a clock pulse having a relatively low value in the discharged state of said ancillary storage capacitor and having a relatively high value upon said ancillary storage capacitor carrying a predetermined minimum charge, said high value enabling conduction of said first semiconductor element for the duration of a driving pulse whereby said main storage capacitor is charged from said supply means; and a second semiconductor element inserted between said junctions for enabling the transfer of charges from said main storage capacitor to said ancillary storage capacitor between clock pulses while preventing a reverse charge transfer in the presence of a clock pulse; said supply means including a third semiconductor element inserted between said other of said conductors and said first semiconductor element for transmitting said clock pulses to said main storage capacitor in the conductive condition of said first semiconductor element.
Claim 2
Dependent Claim
338 words
A circuit arrangement for the storage of a signal voltage of predetermined level, comprising: two conductors connected across a source of recurrent unipolar clock pulses, one of said conductors being grounded; a main storage capacitor and an ancillary storage capacitor both connected to said one of said conductors; supply means including at least said one of said conductors for charging said main storage capacitor with a voltage having the same polarity as said clock pulses; a normally nonconductive first semiconductor element inserted between said supply means and said main storage capacitor on the side opposite said one of said conductors, said first semiconductor element forming a first junction with said main storage capacitor and being provided with a control electrode; a binary capacitor of the same conductivity type as said first semiconductor element inserted between said ancillary storage capacitor and the other of said conductors, said binary capacitor forming with said ancillary storage capacitor a second junction tied to said control electrode, at least one of said junctions being temporarily connectable to an external signaling circuit for the selective charging and discharging of the respective storage capacitor, the capacitance of said binary capacitor in the presence of a clock pulse having a relatively low value in the discharged state of said ancillary storage capacitor and having a relatively high value upon said ancillary storage capacitor carrying a predetermined minimum charge, said high value enabling conduction of said first semiconductor element for the duration of a driving pulse whereby said main storage capacitor is charged from said supply means; and a second semiconductor element inserted between said junctions for enabling the transfer of charges from said main storage capacitor to said ancillary storage capacitor between clock pulses while preventing a reverse charge transfer in the presence of a clock pulse; said supply means including a third semiconductor element inserted between said other of said conductors and said first semiconductor element for transmitting said clock pulses to said main storage capacitor in the conductive condition of said first semiconductor element.
Claim 3
Dependent Claim
19 words
A circuit arrangement as defined in claim 1 wherein said supply means comprises a generator of continuous direct current.
Claim 4
Dependent Claim
53 words
A circuit arrangement as defined in claim 1 wherein said third semiconductor element is a field-effect transistor of the same conductivity type as said first semiconductor element, with a pair of channel electrodes and an insulated gate, said gate and one of said channel electrodes being connected to said other of said conductors.
Claim 5
Dependent Claim
50 words
A circuit arrangement as defined in claim 3 wherein said second semiconductor element is another field-effect transistor of the same conductivity type as said first semiconductor element, with a pair of channel electrodes respectively connected to said junctions and with an insulated gate connected to a point of variable voltage.
Claim 6
Dependent Claim
46 words
A circuit arrangement as defined in claim 4 wherein said point of variable voltage lies on a third conductor connected together with said one of said conductors across a source of unblocking pulses of the same polarity as said clock pulses and offset from the latter.
Claim 7
Dependent Claim
15 words
A circuit arrangement as defined in claim 4 wherein said point is said first junction.
Claim 8
Dependent Claim
30 words
A circuit arrangement as defined in claim 1 wherein said high value of the capacitance of said binary capacitor is substantially smaller than the capacitance of said main storage capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |