Strobe driver including a memory circuit

Claim 2

A strobe driver including a memory circuit, said driver comprising: a field effect transistor memory cell; an output field effect transistor for enabling the generation of strobe signals as a function of data stored in the memory cell, said memory cell having an output connected to the gate electrode of said output field effect transistor and an input for periodically receiving data to be stored during an operating cycle; a boosting field effect transistor device for enabling the charging of a first storage capacitor in said memory cell to a voltage level representing the data on the input of said memory cell, said boosting field effect transistor device including a second storage capacitor for storing a boosted voltage level, and said memory cell further including a load field effect transistor responsive to charge on said second storage capacitor and an isolation field effect transistor which is rendered conductive by the relative charge on said first and second storage capacitors, said isolation transistor comprising part of an electrical circuit for connecting said first storage capacitor to said second storage capacitor for replacing said charge leaked from said second storage capacitor, said replaced charge enabling the enhanced conduction of said load field effect transistor for charging said first storage capacitor.

Claim 3

A strobe driver including a memory circuit, said driver comprising: a field effect transistor memory cell; an output field effect transistor for enabling the generation of strobe signals as a function of data stored in the memory cell, said memory cell having an output connected to the gate electrode of said output field effect transistor and an input for periodically receiving data to be stored during an operating cycle; a load field effect transistor and a first storage capacitor connected in electrical series between a voltage source and a reference voltage level, said output field effect transistor being connected at a common point between said load field effect transistor and said first storage capacitor; a second field effect transistor connected between said common point and a resetting circuit means including a reset field effect transistor for discharging said capacitor to a reference voltage level at the beginning of each operating cycle; a third field effect transistor connected between said second field effect transistor and an input terminal to said memory cell, said third field effect transistor being controlled by said resetting circuit means for enabling data to be written into said memory cell after said memory cell has been reset to said reference data state; and a boosting field effect device connectEd between said third field effect transistor and the gate electrode of said load field effect transistor for providing a boosted voltage level on the gate electrode of said load field effect transistor when data of a certain state is being stored by said memory cell.

Claim 4

A strobe driver including a memory circuit, said driver comprising: a field effect transistor memory cell; an output field effect transistor for enabling the generation of strobe signals as a function of data stored in the memory cell, said memory cell having an output connected to the gate electrode of said output field effect transistor and an input for periodically receiving data to be stored during an operating cycle; a load field effect transistor and a first storage capacitor connected in electrical series between a voltage source and a reference voltage level, said output field effect transistor being connected at a common point between said load field effect transistor and said first storage capacitor; a second field effect transistor connected between said common point and a resetting circuit means including a reset field effect transistor for discharging said capacitor to a reference voltage level at the beginning of each operating cycle; a third field effect transistor connected between said second field effect transistor and an input terminal to said memory cell, said third field effect transistor being controlled by said resetting circuit means for enabling data to be written into said memory cell after said memory cell has been reset to said reference data state; and a boosting field effect device connectEd between said third field effect transistor and the gate electrode of said load field effect transistor for providing a boosted voltage level on the gate electrode of said load field effect transistor when data of a certain state is being stored by said memory cell.

Claim 5

The strobe driver as recited in claim 2 wherein said output field effect transistor is connected in series between a strobe line and a reference voltage level for completing an electrical circuit through said output field effect transistor in response to certain data stored by said memory cell.

Claim 6

The strobe driver recited in claim 2 wherein said resetting circuit means comprises said reset field effect transistor connected to a common point between said second and third field effect transistors and the reference voltage level, said reset field effect transistor having its gate electrode connected through an additional field effect transistor to a clock signal which turns said reset field effect transistor on during a first interval of said operating cycle, the gate electrode of said additional field effect transistor being connected to the output of a further field effect transistor circuit which provides drive voltages during first and second intervals of said operating cycle in response to a cycle initiate signal.

Claim 7

A strobe driver arrangement comprising: a plurality of strobe output lines; a plurality of field effect transistor memory cells, each memory cell including an output node and a storage node for storing information as voltage levels representing first or second logic states; means interconnecting the output nodes of said memory cells with respective ones of said strobe output lines to provide strobe output signals at said strobe output lines, the strobe output signal for a particular strobe output line being a function of the logic state of information stored in the memory cell corresponding to the particular strobe output line; and circuit means controlling operation of the strobe driver arrangement to generate strobe signals representing a desired logic state for sequential application to the respective strobe output lines.

Claim 8

A strobe driver arrangement comprising: a plurality of strobe output lines; a plurality of field effect transistor memory cells, each memory cell including an output node and a storage node for storing information as voltage levels representing first or second logic states; means interconnecting the output nodes of said memory cells with respective ones of said strobe output lines to provide strobe output signals at said strobe output lines, the strobe output signal for a particular strobe output line being a function of the logic state of information stored in the memory cell corresponding to the particular strobe output line; and circuit means controlling operation of the strobe driver arrangement to generate strobe signals representing a desired logic state for sequential application to the respective strobe output lines.

Claim 9

The strobe driver arrangement of claim 5 wherein said means interconnecting includes a plurality of output field effect transistors, each output field effect transistor having its source-drain path connected between a respective strobe output line and a source of reference voltage and its gate electrode connected to the output node of its corresponding memory cell, whereby the conduction of the output transistor is controlled by the voltage at the output node.

Claim 10

The strobe driver arrangement of claim 6 wherein said circuit means includes: means for writing said information into each said memory cell for storage at said storage node; field effect boost means for boosting the stored voltage level at said storage node for the first but not the second of said logic states; a load field effect transistor having its gate electrode connected to said storage node and its source-drain path connected between a voltage source and said output node, said load field effect transistor being rendered conductive by the boosted voltage level at its gate electrode for providing an increased voltage output at said output node for application to the associated output field effect transistor.

Claim 11

The strobe driver arrangement of claim 7 including an isolation field effect transistor having its source-drain path connected between the output and storage nodes, bias means for rendering the isolation transistor non-conductive when the boosted voltage level is present at the storage node, whereby charge leakage from the storage node is prevented and the increased voltage output is maintained at the output node.

Claim 12

The strobe driver arrangement of claim 7 including means for resetting said memory cells to said second of said logic levels at the beginning of an operating cycle.

Claim 13

The strobe driver arrangement of claim 9 wherein said meanS for resetting includes an isolation transistor having its source-drain path connected between the output and storage nodes, a reset field effect transistor having its source-drain path connected between said storage node and a source of reference voltage, said reset field effect transistor when rendered conductive serving to connect the storage node to the source of reference voltage and to connect the output node to the source of reference voltage through the isolation field effect transistor.