Two-clock memory cell

Claim 2

A memory cell having write, reset, and read intervals and comprising: capacitive storage means for storing voltage levels representing first and second logic states of data stored in said memory cell, means for applying a first clock signal to said capacitive storage means during said reset and read intervals of said memory cell, for providing a boost signal at said capacitive storage means during said reset and read intervals for only one of said first and second logic states, a read field effect transistor connected to respond to said boost signal for providing a relatively increased voltage level output for said one logic state.

Claim 3

The memory cell recited in claim 1 further including a write field effect transistor connected between a circuit node and said capacitive storage means for applying said voltage levels to said capacitive storage means during said write interval, said write field effect transistor having its gate electrode connected to a fixed voltage.

Claim 4

The memory cell recited in claim 2 wherein said read field effect transistor has one electrode connected to a fixed voltage level and another electrode connected to said circuit node, said fixed voltage level being applied to said circuit node without a threshold loss across said read field effect transistor in response to said boost signal, and capacitance means at said circuit node for being charged by voltage levels thereat.

Claim 5

The memory cell recited in claim 3 further including an address field effect transistor connected between said circuit node and a data line on which voltages representing data are written into and read from said memory cell, said data line being reset to a reference logic state during a reset interval prior to a read interval, said address field effect transistor having its gate electrode connected to a second clock signal having OR''ed read and write intervals AND''ed with an address interval.

Claim 6

The memory cell recited in claim 4 wherein said read and address field effect transistors have relative impedances for preventing a substantial change in the voltage level at said circuit node when stored data is read from said memory cell, and said capacitance means provides a regenerative charge to replace charge leakage from said capacitive storage means, whereby one of said logic states stored in said cell is regenerated when said cell is not addressed.

Claim 7

The memory cell recited in claim 5 wherein the impedance of said read field effect transistor is small relative to that of said address field effect transistor.

Claim 8

A memory cell comprising, a field effect capacitive storage device having a fixed plate connected to a storage node and a control electrode connected to a first clock signal including a reset and read interval for providing a boosted signal at said storage node as a function of the logic state of data stored in said cell, a read field effect transistor connected between a fixed voltage level and a pre-output node of said memory cell, said read field effect transistor having its gate electrode connected to said storage node for enabling the conduction of said read field effect transistor to be controlled by the boosted signal at said storage node, and a write field effect transistor connected between said pre-output node and said storage node, said write field effect transistor having its gate electrode connected to a fixed voltage level for enabling said write field effect transistor to conduct During a write interval.

Claim 9

A memory cell comprising, a field effect capacitive storage device having a fixed plate connected to a storage node and a control electrode connected to a first clock signal including a reset and read interval for providing a boosted signal at said storage node as a function of the logic state of data stored in said cell, a read field effect transistor connected between a fixed voltage level and a pre-output node of said memory cell, said read field effect transistor having its gate electrode connected to said storage node for enabling the conduction of said read field effect transistor to be controlled by the boosted signal at said storage node, and a write field effect transistor connected between said pre-output node and said storage node, said write field effect transistor having its gate electrode connected to a fixed voltage level for enabling said write field effect transistor to conduct During a write interval.

Claim 10

The memory cell recited in claim 7 further including an address field effect transistor connected between said pre-output node and a data line on which voltage levels representing data are written into and read from said memory cell during read and write intervals, said data line being reset to a reference logic state during a reset interval of said memory cell, said address field effect transistor having its gate electrode connected to a second clock signal having an address interval and the logically ORed combination of read and write intervals.

Claim 11

The memory cell recited in claim 8 and further including, a capacitor connected at said pre-output node, said address and read field effect transistors have relative sizes for preventing a substantial change in the voltage level across said capacitor at said pre-output node during a read interval when the cell is addressed, and said capacitor further providing a regenerative charge to replace charge leakage from said storage device to regenerate a stored logic state when said cell is not addressed.

Claim 12

A memory cell comprising, a storage capacitor connected to a storage node and further disposed in bootstrapped connection between gate and output electrodes of a field effect transistor having input, output, and gate electrodes with said gate electrode connected to said storage node and said input electrode connected to a first clock signal including a reset and read interval for providing a boosted signal at said storage node as a function of the logic state of data stored in said cell, a read field effect transistor connected between a fixed voltage level and a pre-output node of said memory cell, said read field effect transistor having its gate electrode connected to said storage node for enabling the conduction of said read field effect transistor to be controlled by the boosted signal at said storage node, and a write field effect transistor connected between said pre-output node and storage node, said write field effect transistor having its gate electrode connected to a fixed voltage level for enabling said write field effect transistor to conduct during a write interval.

Claim 13

A memory cell comprising, a storage capacitor connected to a storage node and further disposed in bootstrapped connection between gate and output electrodes of a field effect transistor having input, output, and gate electrodes with said gate electrode connected to said storage node and said input electrode connected to a first clock signal including a reset and read interval for providing a boosted signal at said storage node as a function of the logic state of data stored in said cell, a read field effect transistor connected between a fixed voltage level and a pre-output node of said memory cell, said read field effect transistor having its gate electrode connected to said storage node for enabling the conduction of said read field effect transistor to be controlled by the boosted signal at said storage node, and a write field effect transistor connected between said pre-output node and storage node, said write field effect transistor having its gate electrode connected to a fixed voltage level for enabling said write field effect transistor to conduct during a write interval.

Claim 14

The memory cell recited in claim 10 further including an address field effect transistor connected between said pre-output node and a data line on which voltage levels representing data are written into and read from said memory cell during read and write intervals, said data line being reset to a reference logic state during a reset interval of said memory cell, said address field effect transistor having its gate electrode connected to a second clock signal having an address interval and the logically OR''ed combination of read and write intervals.

Claim 15

The memory cell recited in claim 11 and further including, a capacitor connected at said pre-output node, said address and read field effect transistors have relative sizes for preventing a substantial change in the voltage level across said capacitor at said pre-output node during a read interval when the cell is addressed, and said capacitor further providing a regenerative charge to replace charge leakage from said storage device to regenerate a stored logic state when said cell is not addressed.

Claim 16

A memory cell comprising storage means, means for charging the storage means to either one of two levels during a first time interval, means for applying a first clock signal to the storage means during second and third time intervals, thereby to provide, for one but not the other of said levels, a boosted signal at the storage means, and means connected to the storage means so as to be rendered conductive by the boosted signal, and when rendered conductive to provide an enhanced voltage level output during the second and third time intervals.

Claim 17

A memory cell comprising storage means, means for charging the storage means to either one of two levels during a first time interval, means for applying a first clock signal to the storage means during second and third time intervals, thereby to provide, for one but not the other of said levels, a boosted signal at the storage means, and means connected to the storage means so as to be rendered conductive by the boosted signal, and when rendered conductive to provide an enhanced voltage level output during the second and third time intervals.

Claim 18

The memory cell recited in claim 13 wherein said means for charging includes a first field effect transistor connected between a circuit node and said Storage means and having a gate electrode connected to a first fixed voltage for enabling charging of said storage means through said first field effect transistor, and said means connected to the storage means so as to be rendered conductive by the boosted signal includes a second field effect transistor through which a second fixed voltage is connected to said circuit node, whereupon said second fixed voltage is connected to said circuit node without a threshold loss through said second field effect transistor during said second interval thereby insuring the turn-off of said first field effect transistor prior to said third interval.

Claim 19

The memory cell recited in claim 14 including, a third field effect transistor connected between said circuit node and a data line from which data is written into said cell during said first interval and read from said cell during said third interval, said third field effect transistor having a second clock signal applied to its gate electrode during said first and third intervals, when said cell is addressed, whereby data is written into said cell through said first and third field effect transistors during said first time interval and read therefrom through said second and third field effect transistors during said third time interval.

Claim 20

The memory cell recited in claim 15, wherein the impedance of said second field effect transistor is relatively smaller than that of said third field effect transistor to prevent a substantial change in the voltage at said circuit node during said third interval thereby maintaining said first field effect transistor off to prevent dissipation and loss of said boosted signal through said first field effect transistor.

Claim 21

The memory cell recited in claim 13, wherein said storage means includes a conditionally switched capacitor having a control electrode receiving said first clock signal.

Claim 22

The memory cell recited in claim 13, wherein said storage means includes a bootstrapped capacitor connected between the gate and output electrodes of a field effect transistor, the first clock signal being applied to the input electrode of said field effect transistor.

Claim 23

In combination: a circuit line; a circuit node; a storage node; a first field effect transistor connected in a path between the circuit line and the cirucit node; a second field effect transistor connected in a path between the circuit node and the storage node and having a gate electrode connected to receive a fixed voltage level; a third field effect transistor connected in a path between the circuit node and a voltage source and having a gate electrode connected to receive signals from the storage node; first clock means for rendering the first transistor conductive during a first interval to provide an input charge path from the circuit line through the first and second transistors to the storage node for storing a first or second voltage level at the storage node; second clock means for providing a boosted voltage level at the storage node for only one of said first or second stored voltage levels, with the boosted voltage level being sufficient to render the third transistor conductive to connect the voltage source to the circuit node, thereby providing a voltage at the circuit node adequate to insure turn-off of the second transistor, to prevent dissipation and loss of the boosted voltage level through the second transistor; and the first clock means rendering the first transistor conductive after turn-off of the second transistor to provide an output path through the third and first transistors to the circuit line, whereby an output signal is derived at the circuit line representing the stored one of the first or second stored voltage levels.

Claim 24

In combination: a circuit line; a circuit node; a storage node; a first field effect transistor connected in a path between the circuit line and the cirucit node; a second field effect transistor connected in a path between the circuit node and the storage node and having a gate electrode connected to receive a fixed voltage level; a third field effect transistor connected in a path between the circuit node and a voltage source and having a gate electrode connected to receive signals from the storage node; first clock means for rendering the first transistor conductive during a first interval to provide an input charge path from the circuit line through the first and second transistors to the storage node for storing a first or second voltage level at the storage node; second clock means for providing a boosted voltage level at the storage node for only one of said first or second stored voltage levels, with the boosted voltage level being sufficient to render the third transistor conductive to connect the voltage source to the circuit node, thereby providing a voltage at the circuit node adequate to insure turn-off of the second transistor, to prevent dissipation and loss of the boosted voltage level through the second transistor; and the first clock means rendering the first transistor conductive after turn-off of the second transistor to provide an output path through the third and first transistors to the circuit line, whereby an output signal is derived at the circuit line representing the stored one of the first or second stored voltage levels.

Claim 25

The combination recited in claim 19 wherein: the said voltage source connected through the third transistor supplies a fixed voltage level to the circuit node without a threshold loss across the third traNsistor.

Claim 26

The combination recited in claim 19 wherein: the first and third transistors have relative impedances for preventing a substantial change in the voltage at the circuit node during conduction of the third and first transistors thereby holding the second transistor off to prevent loss of the boosted voltage level at the storage node.

Claim 27

The combination recited in claim 19 including, a conditionally switched capacitive storage means having one electrode connected to the storage node and a control electrode connected to the second clock means.

Claim 28

The combination recited in claim 19 including, a fourth field effect transistor having input, output, and gate electrodes with its gate electrode connected to the storage node, a bootstrapped capacitor connected between its gate and output electrodes, and the input electrode connected to receive the second clock means.

Claim 29

In combination: a circuit node; a storage node; a field effect transistor connected in a first path between the circuit node and the storage node and having a gate electrode connected to receive a fixed voltage level for rendering the transistor conductive during a first interval to provide a charge path for charging the storage node to a prescribed voltage level; clock means for providing a boosted voltage level at the storage node when the prescribed voltage level is present; means in a second path between a voltage source and the circuit node and having means connected to respond to the boosted voltage level to supply a circuit node voltage to the circuit node from the voltage source, the level of said circuit node voltage being sufficient to render the field effect transistor non-conductive to thereby prevent dissipation and loss of the boosted signal along the first circuit path through the transistor.

Claim 30

In combination: a circuit node; a storage node; a field effect transistor connected in a first path between the circuit node and the storage node and having a gate electrode connected to receive a fixed voltage level for rendering the transistor conductive during a first interval to provide a charge path for charging the storage node to a prescribed voltage level; clock means for providing a boosted voltage level at the storage node when the prescribed voltage level is present; means in a second path between a voltage source and the circuit node and having means connected to respond to the boosted voltage level to supply a circuit node voltage to the circuit node from the voltage source, the level of said circuit node voltage being sufficient to render the field effect transistor non-conductive to thereby prevent dissipation and loss of the boosted signal along the first circuit path through the transistor.

Claim 31

The combination recited in claim 24 including, means connected in an output path from the circuit node to be rendered conductive by clock signal means applied thereto, the clock signal means being applied after the field effect transistor has been rendered non-conductive.

Claim 32

The combination of claim 24 wherein the storage means is charged to first or second prescribed voltage levels and the clock means provides a boosted voltage level for only one of the first or second prescribed voltage levels.