Circuit producing a common clear signal for erasing selected arrays in a mnos memory system

Claim 1

An integrated circuit comprising: a. first and second semiconductor islands isolated from each other by a PN junction and supported by a common substrate. b. a plurality of memory transistors utilizing said first semiconductor island as a substrate, c. a logic circuit having first and second logic inputs and a logic output, said logic output operatively coupled to the substrate of said memory transistors for applying thereto a first potential in response to first, second, and third preselected permutations of first and second logic signals applied to said logic inputs, and a second potential in response to a fourth preselected permutation of said first and second logic signals applied to said inputs, and including a plurality of semiconductor devices utilizing said second semiconductor island as a substrate, said devices including: (1) a first coupling diode for coupling said first logic input and said logic output, (2) a first switch means operatively coupled between said second logic input and said logic output for operating in response to logic signals, applied to said first logic input, (3) second switch means operatively coupled to said first potential for operating in response to logic signals applied to said second logic input, (4) load means coupled between said second switch means and a third potential for providing an impedance across which a potential is developed, (5) third switch means coupled to said first potential for opening and closing in response to the opening and closing of said second switch means, (6) a second coupling diode for coupling said first potential and said logic output.