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US4097314A
Expired / Lapsed
US
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Method of making a sapphire gate transistor
Assignee: RCA Corp
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Filing: 1976-12-30
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Granted: 1978-06-27
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Expires: 1996-12-30
Abstract
Abstract A method of making an improved aluminum oxide (sapphire) gate field effect transistor wherein the capacitance-voltage characteristic of the transistor is improved by annealing the aluminum oxide at a temperature less than the growth temperature of the aluminum oxide. A transistor annealed at a temperature less than the growth temperature is provided wherein the threshold voltage is the same as if the transistor were annealed at a temperature greater than the growth temperature; the capacitance-voltage characteristic of the transistor exhibiting markedly diminished hysteresis by annealing at a temperature less than the growth temperature.
Inventors
- 👤 Kenneth Mansfield Schlesier
- 👤 Carl William Benyon, Jr.
- 👤 Joseph Michael Shaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D44/00; H10D44/01; H10D44/041; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10D86/00; H10D86/01; H10D86/03; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6516; H10P14/6529; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69391; Y; Y10; Y10S; Y10S148/00; Y10S148/003
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
226 words
A method of making an improved complementary field effect transistor pair comprising the steps of: (a) forming a pair of laterally spaced semiconductor islands of N type and P type conductivity adjacent an insulating substrate; (b) coating the islands with an aluminum oxide layer at a first known temperature; (c) coating the aluminum oxide layer with a polycrystalline silicon layer; (d) coating the polycrystalline silicon layer with a doped oxide; (e) heating the coated polycrystalline silicon layer at a second temperature less than said first temperature for a preselected period to drive the dopant from the doped oxide into the polycrystalline silicon layer; (f) removing the doped oxide; (g) depositing an undoped oxide adjacent the polycrystalline silicon layer; (h) defining said undoped oxide into a mask for gates; (i) removing portions of the polycrystalline silicon layer and the aluminum oxide layer uncovered by the masks; (j) forming a layer of N-doped oxide adjacent the P type island; (k) forming another layer of P-doped oxide adjacent the N type island; (l) heat treating both islands simultaneously at a third temperature no greater than said second temperature for a predetermined period; (m) removing all oxides; (n) oxidizing the wafer at a fourth temperature less than said third temperature for an oxidation period; and (o) annealing the islands in hydrogen at a fifth temperature less than said first temperature.
Claim 2
Independent Claim
226 words
A method of making an improved complementary field effect transistor pair comprising the steps of: (a) forming a pair of laterally spaced semiconductor islands of N type and P type conductivity adjacent an insulating substrate; (b) coating the islands with an aluminum oxide layer at a first known temperature; (c) coating the aluminum oxide layer with a polycrystalline silicon layer; (d) coating the polycrystalline silicon layer with a doped oxide; (e) heating the coated polycrystalline silicon layer at a second temperature less than said first temperature for a preselected period to drive the dopant from the doped oxide into the polycrystalline silicon layer; (f) removing the doped oxide; (g) depositing an undoped oxide adjacent the polycrystalline silicon layer; (h) defining said undoped oxide into a mask for gates; (i) removing portions of the polycrystalline silicon layer and the aluminum oxide layer uncovered by the masks; (j) forming a layer of N-doped oxide adjacent the P type island; (k) forming another layer of P-doped oxide adjacent the N type island; (l) heat treating both islands simultaneously at a third temperature no greater than said second temperature for a predetermined period; (m) removing all oxides; (n) oxidizing the wafer at a fourth temperature less than said third temperature for an oxidation period; and (o) annealing the islands in hydrogen at a fifth temperature less than said first temperature.
Claim 3
Dependent Claim
16 words
A method according to claim 1, wherein the first temperature is no greater than 975° C.
Claim 4
Dependent Claim
24 words
A method according to claim 2, wherein said third temperature is no greater than 950° C and the oxidation period is about 20 minutes.
Claim 5
Dependent Claim
20 words
A method according to claim 1, wherein in step (1) the islands undergo said heat treating for about one hour.
Claim 6
Dependent Claim
18 words
A method according to claim 1, wherein in step (o) the islands are annealed for approximately 20 minutes.
Claim 7
Dependent Claim
15 words
A method according to claim 5, in which said aluminum oxide layer is deposited pyrohydrolytically.
Claim 8
Dependent Claim
25 words
A method according to claim 6, wherein the aluminum oxide layer is deposited at a growth rate of about 50 to 125 A per minute.
Claim 9
Dependent Claim
30 words
A method according to claim 7, wherein the aluminum oxide layer is next slow-cooled in said hydrogen until the temperature of the islands decreases to about 300° to 400° C.
Claim 10
Dependent Claim
22 words
A method according to claim 8, in which said slow cooling is at a rate of 20° to 25° C per minute.
Claim 11
Dependent Claim
213 words
In a method of manufacturing a complementary field effect transistor pair produced by a silicon-on-insulator process comprising the steps of: forming a pair of laterally spaced semmiconductor islands of N-type and P-type conductivity adjacent an insulating substrate; coating the islands with an aluminum oxide layer at a first temperature; coating the aluminum oxide layer with a polycrystalline silicon layer; the improvement comprising the steps of: coating the polycrystalline silicon layer with doped glass and heating at a second temperature less than said first temperature, for a preselected period to drive the dopant into the polycrystalline silicon layer; removing the doped glass; depositing an undoped glass adjacent the polycrystalline silicon layer; defining said undoped glass into a mask for gates; removing portions of the polycrystalline silicon layer and the aluminum oxide layer not covered by the mask; forming a layer of N-doped glass adjacent the P-type island; forming a layer of P-doped glass adjacent the N-type island; heat treating both islands simultaneously at a third temperature no greater than said second temperature for a predetermined period; removing all glasses; oxidizing the wafer in a steam ambient at a fourth temperature less than said third temperature for an oxidation period; and annealing the islands in hydrogen at a fifth temperature less than said first temperature.
Claim 12
Dependent Claim
213 words
In a method of manufacturing a complementary field effect transistor pair produced by a silicon-on-insulator process comprising the steps of: forming a pair of laterally spaced semmiconductor islands of N-type and P-type conductivity adjacent an insulating substrate; coating the islands with an aluminum oxide layer at a first temperature; coating the aluminum oxide layer with a polycrystalline silicon layer; the improvement comprising the steps of: coating the polycrystalline silicon layer with doped glass and heating at a second temperature less than said first temperature, for a preselected period to drive the dopant into the polycrystalline silicon layer; removing the doped glass; depositing an undoped glass adjacent the polycrystalline silicon layer; defining said undoped glass into a mask for gates; removing portions of the polycrystalline silicon layer and the aluminum oxide layer not covered by the mask; forming a layer of N-doped glass adjacent the P-type island; forming a layer of P-doped glass adjacent the N-type island; heat treating both islands simultaneously at a third temperature no greater than said second temperature for a predetermined period; removing all glasses; oxidizing the wafer in a steam ambient at a fourth temperature less than said third temperature for an oxidation period; and annealing the islands in hydrogen at a fifth temperature less than said first temperature.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-26 | 1981-12-26 | 1982-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-26 | 1985-12-26 | 1986-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-26 | 1989-12-26 | 1990-06-27 | $7700.00 | Window Closed / Lapsed |