Patent US4093981A successfully refreshed from Google Patents.
US4093981A
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Data communications preprocessor
Assignee: Unisys Corp
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Filing: 1976-01-28
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Granted: 1978-06-06
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Expires: 1996-01-28
Abstract
Abstract A microprogrammable data communications preprocessor exercises detailed control over a multiplicity of data lines communicating with a microprogrammable central processor while requiring central processor attention on a message basis only. Further minimization of central processor intervention is achieved through a direct memory access channel which permits data transfer directly from the preprocessor to the main memory of the central processor. The preprocessor also includes a line adapter associated with each data communications line for interface purposes, a scratch pad memory for storing data line parameters, and a microprogrammable serial byte microprocessor. Operational speed is enhanced through the inclusion of automatic operation logic which effectively by-passes the serial byte microprocessor for an automatic transfer of two bytes of data.
Inventors
- 👤 John P. McAllister
- 👤 Franklin Theodore Schroeder
- 👤 Charles Terrance Stimson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/14; G06F13/20; G06F13/28; G06F13/282
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
223 words
A data communications preprocessor for processing detailed line procedures between a central processing unit with a main memory and a plurality of data communications lines, each line therein connected to an individually associated data set, said data communications preprocessor comprising: a plurality of line adapter means, each line adapter thereof individually associated with a data communications line in said plurality of data communications lines for facilitating the data communications therewith; serial byte microprocessing means for controlling the processing of detailed data communications line procedures on an individual data communication line basis, said serial byte microprocessing means connected between said central processing unit and said plurality of line adapter means, said serial byte microprocessing means including a serial byte microprocessor, a micromemory means for storing control data bytes and a scratch pad memory for storing data communications parameter information relating to each data communications line in said plurality of data communications lines; direct memory access means for permitting direct transfer of at least one byte of data between said main memory and said micromemory under the control of said serial byte microprocessor; and automatic operation means bypassing said serial byte microprocessor and utilizing said direct memory access means for automatically transferring through said direct memory access means at least one byte of data in parallel between said scratch pad memory and said main memory.
Claim 2
Dependent Claim
223 words
A data communications preprocessor for processing detailed line procedures between a central processing unit with a main memory and a plurality of data communications lines, each line therein connected to an individually associated data set, said data communications preprocessor comprising: a plurality of line adapter means, each line adapter thereof individually associated with a data communications line in said plurality of data communications lines for facilitating the data communications therewith; serial byte microprocessing means for controlling the processing of detailed data communications line procedures on an individual data communication line basis, said serial byte microprocessing means connected between said central processing unit and said plurality of line adapter means, said serial byte microprocessing means including a serial byte microprocessor, a micromemory means for storing control data bytes and a scratch pad memory for storing data communications parameter information relating to each data communications line in said plurality of data communications lines; direct memory access means for permitting direct transfer of at least one byte of data between said main memory and said micromemory under the control of said serial byte microprocessor; and automatic operation means bypassing said serial byte microprocessor and utilizing said direct memory access means for automatically transferring through said direct memory access means at least one byte of data in parallel between said scratch pad memory and said main memory.
Claim 3
Dependent Claim
58 words
The data communications preprocessor according to claim 1 wherein said scratch pad memory includes a portion of memory individually associated with each data communication line in said plurality of data communications lines whereby all stored data communications parameter information of each individual data communications line is stored in said portion of said scratch pad memory individually associated therewith.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-05 | 1981-12-05 | 1982-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-05 | 1985-12-05 | 1986-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-05 | 1989-12-05 | 1990-06-06 | $7700.00 | Window Closed / Lapsed |