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US4092735A
Expired / Lapsed
US
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Static memory cell using field implanted resistance
Assignee: Texas Instruments Inc
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Filing: 1976-12-27
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Granted: 1978-05-30
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Expires: 1996-12-27
Abstract
Abstract A cell for a semiconductor memory of the static type employs two conventional MOS transistors along with a field implanted resistance which functions as a grounded-gate junction FET. Along with other resistor elements, these devices provide a grounded-gate amplifier with voltage gain and a source follower, creating a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:13
CPC Classifications
H; H10; H10B; H10B10/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39; G11C11/40; G11C11/41; G11C11/412; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/817; H10D84/82; H10W; H10W20/00; H10W20/01; H10W20/021; H10B10/15
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
152 words
A semiconductor integrated circuit comprising first and second MOS transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels, the source-drain path of the second transistor being connected between the first node and a voltage supply, the gate of the second transistor being connected to a second node, an impedance element connecting the first node to the second node, the impedance element exhibiting a low impedance state when the voltage on the first and second nodes is relatively low and exhibiting a high impedance state when the voltage on the first and second nodes is relatively high, first impedance means connecting the second node to a voltage supply, and second impedance means connecting the first node to reference potential.
Claim 2
Dependent Claim
152 words
A semiconductor integrated circuit comprising first and second MOS transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels, the source-drain path of the second transistor being connected between the first node and a voltage supply, the gate of the second transistor being connected to a second node, an impedance element connecting the first node to the second node, the impedance element exhibiting a low impedance state when the voltage on the first and second nodes is relatively low and exhibiting a high impedance state when the voltage on the first and second nodes is relatively high, first impedance means connecting the second node to a voltage supply, and second impedance means connecting the first node to reference potential.
Claim 3
Dependent Claim
17 words
A circuit according to claim 1 wherein the impedance element functions as a grounded-gate field effect transistor.
Claim 4
Dependent Claim
27 words
A circuit according to claim 2 wherein the impedance element is a region within the semiconductor material formed by ion implant and having a low impurity concentration.
Claim 5
Dependent Claim
22 words
A circuit according to claim 3 wherein the region which forms the impedance element is buried beneath a thick thermal oxide layer.
Claim 6
Dependent Claim
36 words
A circuit according to claim 2 wherein the impedance element and the first impedance means provide a grounded-gate amplifier having voltage gain with the first node as an input and the second node as an output.
Claim 7
Dependent Claim
33 words
A circuit according to claim 5 wherein the second transistor and the second impedance means provide a source follower with the second node as an input and the first node as an output.
Claim 8
Dependent Claim
51 words
A circuit according to claim 1 wherein the source of logic levels is a bit line in a memory array, the different source of logic levels is an address line in the memory array, and the first node is a storage node capable of sustaining a logic "1" or logic "0".
Claim 9
Dependent Claim
101 words
A storage cell comprising an address line, a data line, a storage node, a first controlled switching device having a current path connecting the data line to the storage node and being controlled by the address line, a voltage supply, a second controlled switching device connecting the storage node to the voltage supply, voltage-controlled resistance means connecting the storage node to a refresh node, the refresh node being connected to the control element of the second switching device, first impedance means for connecting the voltage supply to the refresh node, and second impedance means connecting the storage node to reference potential.
Claim 10
Dependent Claim
101 words
A storage cell comprising an address line, a data line, a storage node, a first controlled switching device having a current path connecting the data line to the storage node and being controlled by the address line, a voltage supply, a second controlled switching device connecting the storage node to the voltage supply, voltage-controlled resistance means connecting the storage node to a refresh node, the refresh node being connected to the control element of the second switching device, first impedance means for connecting the voltage supply to the refresh node, and second impedance means connecting the storage node to reference potential.
Claim 11
Dependent Claim
20 words
A storage cell according to claim 8 wherein the resistance means is responsive to the voltage on the storage node.
Claim 12
Dependent Claim
36 words
A storage cell according to claim 9 wherein the resistance means exhibits a large change in resistance when the voltage at its terminals changes from near reference potential to near the value of the voltage supply.
Claim 13
Dependent Claim
26 words
A storage cell according to claim 8 wherein the controlled switching devices are MOS transistors and the resistance means is a field-implanted junction-type field effect transistor.
Claim 14
Dependent Claim
35 words
A storage cell according to claim 8 wherein the cell is within a semiconductor integrated circuit and the resistance means is formed by an elongated region in the semiconductor material of low net impurity concentration.
Claim 15
Dependent Claim
36 words
A storage cell according to claim 10 wherein the second switching device and the second impedance means provide a source follower stage with the refresh node as its input and the storage node as its output.
Claim 16
Dependent Claim
36 words
A storage cell according to claim 13 wherein the resistance means and the first impedance means provide a grounded-gate amplifier with voltage gain, the storage node being its input and the refresh node being its output.
Claim 17
Dependent Claim
36 words
A storage cell according to claim 14 wherein the source follower stage and the grounded-gate amplifier provide a static flip-flop which is stable with either a logic "1" or a logic "0" on the storage node.
Claim 18
Dependent Claim
23 words
A storage cell according to claim 15 wherein the switching devices are MOS transistors and the resistance means resembles a junction field-effect transistor.
Claim 19
Dependent Claim
21 words
A storage cell according to claim 16 wherein the resistance means comprises an ion-implanted region beneath a thick thermally-grown oxide layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-29 | 1981-11-28 | 1982-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-29 | 1985-11-28 | 1986-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-29 | 1989-11-28 | 1990-05-30 | $7700.00 | Window Closed / Lapsed |