One-bit-out-of-N-bit checking circuit

Claim 2

A one-out-of-n check circuit comprising k successive, serially connected detector levels, a first one of the detector levels having n input signal lines and a plurality of logic blocks, each successive higher one of the detector levels having one half the number of input signal lines and logic blocks as does the next lower detector level, the input signal lines being arranged in pairs and a different one of the logic blocks in each detector level connected to each separate pair of input signal lines, each logic block including first and second outputs, means in each logic block responsive to the presence of excitation signals on both input signal lines of the pair for generating an error condition indication at the first output of the logic block, means in each logic block responsive to the presence of an excitation signal on one input signal line of the pair for propagating the excitation signal via the second output of the logic block to an input signal line of the next successively higher detector level, the logic block in the k th detector level providing at its second output a first output of the check circuit and being responsive to the presence of an excitation signal on one and only one of the input signal lines to the k th detector level for generating an excitation signal at its second output and means for connecting the first output of each logic block to a second output of the check circuit so as to provide to the second output of the check circuit an error signal responsive to the error condition indication at the first output of any logic block.

Claim 3

A one-out-of-n check circuit in accordance with claim 1 wherein the generating and propagating means includes a logical NAND gate connected in parallel with a logical EXCLUSIVE-OR gate, the logical NAND gate being responsive to the presence of excitation signals on both input signal lines of the pair of input signal lines for generating the error condition indication and the logical EXCLUSIVE-OR gate being responsive to the presence of an excitation signal on one input signal line of the pair of input signal lines for propagating the excitation signal.

Claim 4

A one-out-of-n check circuit in accordance with claim 1, wherein the number of logic blocks included in the first one of the detector levels is equal to 2 k-1 , successively higher detector levels having one half the number of logic blocks as does the next lower detector level and the k th detector level having one and only one logic block.

Claim 5

In a one-out-of-n check circuit, k successive serially connected detector levels, a first one of the detector levels having n input signal lines and successively higher ones of the detector levels being serially connected to the next lower detector level and having one half the number of input signal lines as does the next lower detector level, the input signal lines to each detector level being grouped in pairs, the check circuit including, a plurality of logic blocks, each logic block being connected to a separate pair of input signal lines and including first means for generating the logical NAND function of excitation signals present on the pair of input signal lines and second means for generating the logical EXCLUSIVE-OR function of the excitation signals present on the pair of input signal lines, and means responsive to the first means of each block for providing a first check circuit output indicative of an error condition and responsive to the second means for propagating the excitation signals to successively higher detector levels and for providing a second check circuit output from the k th detector level.

Claim 6

In a one-out-of-n check circuit, k successive serially connected detector levels, a first one of the detector levels having n input signal lines and successively higher ones of the detector levels being serially connected to the next lower detector level and having one half the number of input signal lines as does the next lower detector level, the input signal lines to each detector level being grouped in pairs, the check circuit including, a plurality of logic blocks, each logic block being connected to a separate pair of input signal lines and including first means for generating the logical NAND function of excitation signals present on the pair of input signal lines and second means for generating the logical EXCLUSIVE-OR function of the excitation signals present on the pair of input signal lines, and means responsive to the first means of each block for providing a first check circuit output indicative of an error condition and responsive to the second means for propagating the excitation signals to successively higher detector levels and for providing a second check circuit output from the k th detector level.

Claim 7

In a one-out-of-n check circuit, k successive serially connected detector levels, each detector level including a plurality of logic blocks with a first detector level having a number of logic blocks x, where x = 2 k-1 , successively higher detector levels having one half the number of logic blocks as does the next lower detector level, and the k th detector level having one logic block, each logic block in the check circuit having two inputs connected to a separate pair of detector level input signal lines and including a two input NAND gate connected to the separate pair of input signal lines, and a two input EXCLUSIVE-OR gate connected to the separate pair of input signal lines, the NAND gate having an output responsive to the presence of excitation signals on both input signal lines of the pair of input signal lines for generating a first logic block output signal, and the EXCLUSIVE-OR gate included in the logic blocks having an output responsive to the presence of an excitation signal on one input signal line of the pair of input signal lines which EXCLUSIVE-OR gate output is a second logic block output, the second logic block output of each of the logic blocks of the first k -1 detector levels being connected for transmitting the one excitation signal to the logic blocks in the next higher detector level, the second logic block output of the logic block included in the k th detector level being responsive to the presence of an excitation signal on one input signal line of the pair of input signal lines for generating a first output signal of the check circuit, and the first output of each logic block in the check circuit being connected to form a second output of the check circuit responsive to the presence of excitation signals on both input signal lines of the pair of input signal lines connected to the inputs of any logic block in the check circuit.

Claim 8

In a one-out-of-n check circuit, k successive serially connected detector levels, each detector level including a plurality of logic blocks with a first detector level having a number of logic blocks x, where x = 2 k-1 , successively higher detector levels having one half the number of logic blocks as does the next lower detector level, and the k th detector level having one logic block, each logic block in the check circuit having two inputs connected to a separate pair of detector level input signal lines and including a two input NAND gate connected to the separate pair of input signal lines, and a two input EXCLUSIVE-OR gate connected to the separate pair of input signal lines, the NAND gate having an output responsive to the presence of excitation signals on both input signal lines of the pair of input signal lines for generating a first logic block output signal, and the EXCLUSIVE-OR gate included in the logic blocks having an output responsive to the presence of an excitation signal on one input signal line of the pair of input signal lines which EXCLUSIVE-OR gate output is a second logic block output, the second logic block output of each of the logic blocks of the first k -1 detector levels being connected for transmitting the one excitation signal to the logic blocks in the next higher detector level, the second logic block output of the logic block included in the k th detector level being responsive to the presence of an excitation signal on one input signal line of the pair of input signal lines for generating a first output signal of the check circuit, and the first output of each logic block in the check circuit being connected to form a second output of the check circuit responsive to the presence of excitation signals on both input signal lines of the pair of input signal lines connected to the inputs of any logic block in the check circuit.