Checking circuit for a 1-out-of-n decoder

Claim 2

A checking circuit for a 1-out-of-n binary decoder where n 2K, n being the number of decoder outputs 0 through n-1 that are to be checked on the associated n decoder output lines 0 through n-1 and n, K being positive integers wherein there is utilized for identification of the input lines associated therewith a binary table of n rows, 0 through n-1, and K columns, 0 through K-1, with a binary 0 or 1 entry at each of the nK row-column intersections, said checking circuit comprising: nK separate input lines, said nK separate input lines arranged into K sets of n column-associated input lines and n sets of K row-associated input lines, each of said nK separate input lines associated with and identified by an associated one of said nK binary entries of said binary table for being identified either as a 0-associated input line or as a 1associated input line as determined by the 0 or 1 binary entry at the associated one of said nK binary entries; means parallel intercoupling the K input lines of each of said n sets of K row-associated input lines for receiving the associated ones of said n decoder outputs; K pairs of column-associated OR gates, each pair comprised of a 0-associated OR gate and a 1-associated OR gate; K column-associated AND gates; a <1 OR gate; a >1 OR gate; means coupling the 0-associated input lines and the 1-associated input lines of each of said K sets of n column-associated input lines to the 0-associated OR gate and the 1-associated OR gate, respectively, of the associated pair of the K pairs of columnassociated OR gates; means coupling the outputs of each pair of the K pairs of column-associated OR gates to an associated one of the K columnassociated AND gates; means coupling the outputs of the K column-associated AND gates to said >1 OR gate for generating the >1 output signal only when two or more of said n decoder outputs are active; means coupling the outputs of any pair of the K pairs of columnassociated OR gates to said <1 OR gate for generating the <1 output signal only when none of said n decoder outputs is active.

Claim 3

A checking circuit for a 1-out-of m binary decoder where m<n 2K, m being the number of decoder outputs 0 through m-1 that are to be checked on the associated m decoder output lines 0 through m-1 and m, n, K being positive integers wherein there is utilized for identification of the input lines associated therewith a binary table of n rows, 0 through n-1, and K columns, 0 through K-1, with a binary 0 or 1 entry at each of the nK row-column intersections, said checking circuit comprising: mK separate input lines, said mK separate input lines arranged into K sets of m column-associated input lines and m contiguous sets of K row-associated input lines, each of said mK separate input lines associated with and identified by an associated one of the mK binary entries in the associated m contiguous sets of K row-associated binary entries of said binary table for being identified either as a 0-associated input line or as a 1-associated input line as determined by the 0 or 1 binary entry at the associated one of said mK binary entries; means parallel intercoupling the K input lines of each of said m sets of K row-associated input lines for receiving the associated ones of said n decoder outputs; K pairs of column-associated OR gates, each pair comprised of a 0-associated OR gate and a 1-associated OR gate; K column-associated AND gates; a <1 OR gate; a >1 OR gate; means coupling the 0-associated input lines and the 1-associated input lines of each of said K sets of m column-associated input lines to the 0-associated OR gate and the 1-associated OR gate, respectively, of the associated pair of the K pairs of column-associated OR gates; means coupling the outputs of each pair of the K pairs of column-associated OR gates to an associated one of the K column-associated AND gates; means coupling the outputs of the K column-associated AND gates to said >1 OR gate for generating the >1 output signal only when two or more of said m decoder outputs are active; means coupling the outputs of any one pair of the K pairs of column-associated OR gates to said <1 OR gate for generating the <1 output signal only when none of said m decoder outputs is active.

Claim 4

A checking circuit for a 1-out-of m binary decoder where m<n 2K, m being the number of decoder outputs 0 through m-1 that are to be checked on the associated m decoder output lines 0 through m-1 and m, n, K being positive integers wherein there is utilized for identification of the input lines associated therewith a binary table of n rows, 0 through n-1, and K columns, 0 through K-1, with a binary 0 or 1 entry at each of the nK row-column intersections, said checking circuit comprising: mK separate input lines, said mK separate input lines arranged into K sets of m column-associated input lines and m contiguous sets of K row-associated input lines, each of said mK separate input lines associated with and identified by an associated one of the mK binary entries in the associated m contiguous sets of K row-associated binary entries of said binary table for being identified either as a 0-associated input line or as a 1-associated input line as determined by the 0 or 1 binary entry at the associated one of said mK binary entries; means parallel intercoupling the K input lines of each of said m sets of K row-associated input lines for receiving the associated ones of said n decoder outputs; K pairs of column-associated OR gates, each pair comprised of a 0-associated OR gate and a 1-associated OR gate; K column-associated AND gates; a <1 OR gate; a >1 OR gate; means coupling the 0-associated input lines and the 1-associated input lines of each of said K sets of m column-associated input lines to the 0-associated OR gate and the 1-associated OR gate, respectively, of the associated pair of the K pairs of column-associated OR gates; means coupling the outputs of each pair of the K pairs of column-associated OR gates to an associated one of the K column-associated AND gates; means coupling the outputs of the K column-associated AND gates to said >1 OR gate for generating the >1 output signal only when two or more of said m decoder outputs are active; means coupling the outputs of any one pair of the K pairs of column-associated OR gates to said <1 OR gate for generating the <1 output signal only when none of said m decoder outputs is active.

Claim 5

The checking circuit of claim 2 in which the number of input lines coupled to each of said column-associated 0-OR gates and said column-associated 1-OR gates is balanced by identifying the m contiguous sets of K row-associated input lines with the m contiguous sets of K row-associated binary entries with the substanTial center of the n sets of K row-associated binary entries of said binary table.