Circuit for detecting the presence of other than one-bit-out-of-n bits

Claim 2

A circuit for monitoring a plurality of input signal lines for a valid condition defined by the presence of a single signal on any one of the plurality of input signal lines comprising: first gating circuit means for receiving signals from said input signal lines and combining the signals in a matrix arrangement, including two separate groups of a plurality of matrix output signal lines and arranged so that a signal on any of the input signal lines is transmitted to a matrix output signal line in each of the two groups, and second gating circuit means connected to the matrix output signal lines of both groups for providing a first control signal indicating a valid condition when only one matrix output line in each of the groups has a signal thereon and a second control signal indicating an error condition when none or more than one of the matrix output lines in either of the groups have signals thereon.

Claim 3

A circuit as defined in claim 1 wherein said second gating circuit means includes: third gating circuit means connected to the matrix output signal lines of a first one of saiD groups so that the third gating circuit means provides a third signal indicating a signal is present on only one of the matrix output signal lines in the first group; fourth gating circuit means connected to the matrix output signal lines of the second one of said groups so that the fourth gating circuit means provides a fourth signal indicating a signal is present on only one of the matrix signal lines in the second group, and fifth gating circuit means connected to said third and fourth gating circuit means for providing said first control signal in response to the third and fourth signals from both the third and fourth gating circuit means, and said second control signal in absence of at least one of said third and fourth control signals.

Claim 4

A circuit as defined in claim 1 wherein said second gating circuit means includes: third gating circuit means connected to the matrix output signal lines of a first one of said groups so that the third gating circuit means provides a third signal having a first form if a signal is present on only one of the matrix output signal lines and a second form if a signal is present on more than one matrix output signal line; fourth gating circuit means connected to the matrix output signal lines of the second one of said groups so that the fourth gating circuit means provides a fourth signal having a first form if a signal is present on only one of the matrix output signal lines and a second form if a signal is present on more than one of the matrix output signal lines; fifth gating circuit means connected to the matrix signal lines of at least one of said first and second groups for providing a fifth signal when no signals are present on any one of the connected matrix output signal lines, and sixth gating circuit means connected to said third, fourth and fifth gating circuit means for providing said first control signal in response to the first form of both of said third and fourth signals, and said second control signal in response to at least one of the fifth signals, second form of the third signal and second form of the fourth signal.

Claim 5

A circuit for monitoring a plurality of input signal lines for a valid condition defined by the presence of a single signal on any one of the plurality of input signal lines comprising: a plurality of gating circuit means connected to separate groups of input circuit lines, each of said gating circuit means providing a first signal if a signal is present on more than one input signal line connected thereto, a second signal if no signals are present on any of the input signal lines connected thereto, and a third signal if one signal is present on only one of the input signal lines connected thereto; circuit means connected to said plurality of gating circuit means responsive to the presence of third signals from at least two of said gating circuit means for generating a fourth signal; circuit means connected to said plurality of gating circuit means for detecting the presence of a second signal from each of the plurality of gating circuits for generating a fifth signal, and circuit means responsive to any one of said first, fourth and fifth signals for providing an error signal.

Claim 6

A circuit for monitoring a plurality of input signal lines for a valid condition defined by the presence of a single signal on any one of the plurality of input signal lines comprising: a plurality of gating circuit means connected to separate groups of input circuit lines, each of said gating circuit means providing a first signal if a signal is present on more than one input signal line connected thereto, a second signal if no signals are present on any of the input signal lines connected thereto, and a third signal if one signal is present on only one of the input signal lines connected thereto; circuit means connected to said plurality of gating circuit means responsive to the presence of third signals from at least two of said gating circuit means for generating a fourth signal; circuit means connected to said plurality of gating circuit means for detecting the presence of a second signal from each of the plurality of gating circuits for generating a fifth signal, and circuit means responsive to any one of said first, fourth and fifth signals for providing an error signal.

Claim 7

A circuit as defined in claim 4 wherein each of said gating circuit means includes: a first gating circuit for receiving signals from the input signal lines connected thereto and combining the signals in a matrix arrangement including two separate groups of a plurality of matrix output signal lines arranged so that a signal on any of the input signal lines connected thereto is transmitted to a matrix output signal line in each of the two groups, and a second gating circuit connected to the matrix output signal lines of both groups and being responsive to signals thereon to provide said first, second and third signals.

Claim 8

A circuit as defined in claim 5 wherein said second gating circuit includes: a third gating circuit connected to the matrix output signal lines of a first one of said groups so that the third gating circuit provides a sixth signal indicating a signal is present on only one of the matrix output signal lines in the first group; a fourth gating circuit connected to the matrix output signal lines of the second one of said groups so that the fourth gating circuit provides a seventh signal indicating a signal is present on only one of the matrix signal lines in the second group, and a fifth gating circuit connected to said third and fourth gating circuit responsive to said sixth and seventh signals for providing said first, second and third signals.

Claim 9

A circuit as defined in claim 5 wherein said second gating circuit includes: a third gating circuit connected to the matrix output signal lines of a first one of said groups so that the third gating circuit provides a sixth signal having a first form if a signal is present on only one of the matrix output signal lines and a second form if a signal is present on more than one matrix output signal line; a fourth gating circuit connected to the matrix output signal lines of the second one of said groups so that the fourth gating circuit provides a seventh signal having a first form if a signal is present on only one of the matrix output signal lines and a second form if a signal is present on more than one of the matrix output signal lines; a fifth gating circuit connected to the matrix signal lines of at least one of said first and second groups for providing said second signal when no signals are present on any one of the connected matrix output signal lines, and sixth gating circuit connected to said third and fourth gating circuits for providing said third signal in response to the first form of both of said sixth and seventh signals, and said first signal in response to at least one of the second form of the sixth signal and second form of the seventh signal.