Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
165 words
A circuit arrangement for simulating the operation of a dynamic decoder circuit which comprises parallel connected capacitively loaded decoder transistors which receive inverted and non-inverted address signals, a pre-charging transistor, switching elements, and a capacitively loaded end stage connected to and disconnected from the decoder transistors via the switching elements to respectively sample the output signal of the decoder transistors and pre-charge the end stage, said circuit arrangement comprising: discharge transistors, simulating the decoder transistors, connected in parallel and including control inputs for receiving at least some of the address signals, and a node at one parallel connection point; a pre-charging transistor connected to said node and to a voltage supply; a first varactor diode connected between said node and the voltage supply; a second varactor diode connected between a voltage supply and said end stage to simulate the capacitive load of the end stage; and circuit means connected between said second varactor and said node and corresponding to the switching elements of the decoder.
Claim 2
Dependent Claim
165 words
A circuit arrangement for simulating the operation of a dynamic decoder circuit which comprises parallel connected capacitively loaded decoder transistors which receive inverted and non-inverted address signals, a pre-charging transistor, switching elements, and a capacitively loaded end stage connected to and disconnected from the decoder transistors via the switching elements to respectively sample the output signal of the decoder transistors and pre-charge the end stage, said circuit arrangement comprising: discharge transistors, simulating the decoder transistors, connected in parallel and including control inputs for receiving at least some of the address signals, and a node at one parallel connection point; a pre-charging transistor connected to said node and to a voltage supply; a first varactor diode connected between said node and the voltage supply; a second varactor diode connected between a voltage supply and said end stage to simulate the capacitive load of the end stage; and circuit means connected between said second varactor and said node and corresponding to the switching elements of the decoder.
Claim 3
Dependent Claim
29 words
The circuit arrangement of claim 1, wherein said first varactor includes a control input connected to the voltage supply to provide that said first varactor is always capacitively active.
Claim 4
Dependent Claim
60 words
The circuit arrangement of claim 1, wherein the end stage of the decoder includes an inverter and capacitive coupling between a control input of the inverter and one terminal of a controlled path thereof, and comprising: a third varactor connected to a voltage supply to provide that said second varactor is capacitively effective only when said third varactor is active.
Claim 5
Dependent Claim
25 words
The circuit arrangement of claim 1, wherein: the capacitance of said first varactor corresponds to the capacitance of the diffusion capacitance of the decoder circuit.
Claim 6
Dependent Claim
27 words
The circuit arrangement of claim 1, wherein: said pair of discharge transistors are dimensioned in precisely the same manner as the decoder transistors of the decoder circuit.