Patent US4084108A successfully refreshed from Google Patents.
US4084108A
Expired / Lapsed
US
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Integrated circuit device
Assignee: NEC Corp
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Filing: 1975-11-04
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Granted: 1978-04-11
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Expires: 1995-11-04
Abstract
Abstract A semiconductor integrated circuit 3 transistor/bit cell includes two MOS transistors having superposed and insulated gate electrodes overlying the substrate at the portion between the diffused regions, so that the memory can be fabricated in a reduced area.
Inventors
- 👤 Shoji Fujimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; H10B; H10B12/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
251 words
A semiconductor integrated circuit device comprising a semiconductor substrate of a first conductivity type; first, second, third and fourth regions of a second conductivity type formed on one major surface of said substrate; a first insulating film formed on said surface of said substrate between said first and second regions; a first electrode formed on said first insulating film; a second insulating film formed on said surface of said substrate between said third and fourth regions; a second electrode formed on said second insulating film and extending from an area above the edge of said third region to an area above said surface of said substrate intermediate said third and fourth regions; a third electrode formed on said second insulating film and extending from an area above the edge of said fourth region to an area above said surface of said substrate intermediate said third and fourth regions; said second and third electrodes being partly superposed on each other, a third insulating film interposed between the superposed portions of said second and third electrodes, means for connecting said second region to said second electrode; a write address line connected to said first electrode; and a read address line connected to said third electrode; a first capacitance being formed by said second and third electrodes and said third insulating film between said second and third electrodes; and a second capacitance being formed between said second electrode and said substrate; wherein an information on said first region is stored in said second capacitance.
Claim 2
Dependent Claim
251 words
A semiconductor integrated circuit device comprising a semiconductor substrate of a first conductivity type; first, second, third and fourth regions of a second conductivity type formed on one major surface of said substrate; a first insulating film formed on said surface of said substrate between said first and second regions; a first electrode formed on said first insulating film; a second insulating film formed on said surface of said substrate between said third and fourth regions; a second electrode formed on said second insulating film and extending from an area above the edge of said third region to an area above said surface of said substrate intermediate said third and fourth regions; a third electrode formed on said second insulating film and extending from an area above the edge of said fourth region to an area above said surface of said substrate intermediate said third and fourth regions; said second and third electrodes being partly superposed on each other, a third insulating film interposed between the superposed portions of said second and third electrodes, means for connecting said second region to said second electrode; a write address line connected to said first electrode; and a read address line connected to said third electrode; a first capacitance being formed by said second and third electrodes and said third insulating film between said second and third electrodes; and a second capacitance being formed between said second electrode and said substrate; wherein an information on said first region is stored in said second capacitance.
Claim 3
Dependent Claim
23 words
The semiconductor integrated memory circuit device as claimed in claim 1, further comprising a digit line connected to said first and fourth regions.
Claim 4
Dependent Claim
32 words
The semiconductor integrated memory circuit device as claimed in claim 1, further comprising a write digit line connected to said first region, and a read digit line connected to said fourth region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-10 | 1981-10-10 | 1982-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-10 | 1985-10-10 | 1986-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-10 | 1989-10-10 | 1990-04-11 | $7700.00 | Window Closed / Lapsed |