Digital differential amplifier for ccd arrangements

Claim 2

A digital differential amplifier comprising a first voltage supply terminal and a second voltage supply terminal, an input terminal, an output terminal, a first transistor connected to said input terminal via a first terminal of its source-drain-channel, said first transistor having a gate terminal for connection to a first control potential terminal, a first capacitance connected between said input terminal and said first voltage supply terminal, a circuit node point, a second transistor connected between said circuit node point and said output terminal, said second transistor having a gate connected to said input terminal, a third transistor connected between said second voltage supply terminal and said circuit node point, said third transistor having a gate terminal for connection to a second control potential terminal, a fourth transistor connected between said second voltage supply terminal and said output terminal, said fourth transistor having its gate connected to said circuit node point, a second capacitance connected between said output terminal and said first voltage supply terminal, a third capacitance connected between said circuit node point and said first voltage supply terminal, a current sink connected between said output terminal and a third voltage supply terminal.

Claim 3

A digital differential amplifier according to claim 1 in which said first transistor has a second terminal of its source-drain-channel connected to said circuit node.

Claim 4

A digital differential amplifier according to claim 1 in which said first transistor has a second terminal of its source-drain-channel connected to said second voltage supply terminal.

Claim 5

A digital differential amplifier according to claim 1 having additionally a data input terminal and a fifth transistor connected between said data input terminal and said amplifier input point, said fifth transistor having its gate terminal connected to a clock pulse terminal.

Claim 6

A digital differential amplifier according to claim 1 in which said current sink includes a second circuit node, a fifth transistor connected between said output terminal and said third voltage supply terminal, having its gate input connected to said second circuit node; a sixth transistor connected between said second voltage supply terminal and said second circuit node having its gate input connected to said second voltage supply terminal; a seventh transistor having its gate input connected to said second circuit node and connected between said second circuit node and said third voltage supply terminal.

Claim 7

A digital differential amplifier according to claim 1 with said current sink comprising a second circuit node, a first transistor connected between said output terminal and said third voltage supply terminal, said fifth transistor having a gate input connected to said third voltage supply terminal; a sixth transistor connected between said output terminal and said first voltage supply terminal having its gate input connected to said second circuit node; a seventh transistor connected between said second voltage supply terminal and said second circuit node, said seventh transistor having its gate input connected to said second voltage terminal; an eighth transistor connected between said second circuit node and said first voltage supply terminal, said eighth transistor having its gate input connected to said second circuit node.

Claim 8

The method of using the CCD detection system as set forth in claim 1 to regenerate stored charges detected at the output of a first charge coupled device and transferring that regenerated charge to the input of a second charge coupled device which comprises: pre-charging said first and second capacitances to said output voltage of said first voltage supply by turning on said first and second transistors with said first and second control voltages; turning off said first transistor and turning on a first output gate terminal of said first charge coupled device and permitting the absence of charge at the output of said first charge coupled device to discharge said first capacitance; turning off said third transistor because said charge is drained off of said first capacitance and turning off said second transistor permitting said second capacitance to hold on said fourth transistor resulting in output voltage continuing to appear at said output terminal and maintaining a charge on said third capacitance; turning on a first input gate electrode of a second charge coupled device to detect the charge present on said third capacitance; conversely, turning on a first output gate terminal of said first charge coupled device and permitting the presence of charge to not discharge said first capacitance; holding on said third transistor because said charge on said first capacitance is not drained off and turning off said second transistor permitting said second capacitance to be discharged turning off said fourth transistor resulting in said third capacitance being discharged and a decline in voltage appearing at said output terminal; and turning on a first input gate terminal of said second charge coupled device to detect the absence of charge on said third capacitance.

Claim 9

The method according to claim 7, wherein said second control voltage is a pulse voltage of minimal magnitude such that said second and fourth transistors properly conduct and said output voltage is properly detectable at said input gate terminal of said second charge coupled device.

Claim 10

A CCD detection system comprising a digital differential amplifier and two charge coupled devices for regenerating stored charges detected at the output of the first charge coupled device and transferring that regenerated charge to the input of a second charge coupled device, a digital differential amplifier comprising a first voltage supply terminal and a second voltage supply terminal, an input terminal, an output terminal, a first transistor connected to said input terminal via a first terminal of its source-drain-channel, said first transistor having a gate terminal for connection to a first control potential terminal, a first capacitance connected between said input terminal and said first voltage supply terminal, a circuit node point, a second transistor connected between said circuit node point and said output terminal, said second transistor having a gate connected to said input terminal, a third transistor connected between said second voltage supply terminal and said circuit node point, said third transistor having a gate terminal for connection to a second control potential terminal, a fourth transistor connected between said second voltage supply terminal and said output terminal, said fourth transistor having its gate connected to said circuit node point, a second capacitance connected between said output terminal and said first voltage supply terminal, a third capacitance connected between said circuit node point and said first voltage supply terminal, a current sink connected between said output terminal and a third voltage supply terminal, said input terminal to said digital differential amplifier being connected to an output terminal of a first charge coupled device and said output terminal of said differential amplifier being connected to an input terminal of a second charge coupled device.

Claim 11

A CCD detection system comprising a digital differential amplifier and two charge coupled devices for regenerating stored charges detected at the output of the first charge coupled device and transferring that regenerated charge to the input of a second charge coupled device, a digital differential amplifier comprising a first voltage supply terminal and a second voltage supply terminal, an input terminal, an output terminal, a first transistor connected to said input terminal via a first terminal of its source-drain-channel, said first transistor having a gate terminal for connection to a first control potential terminal, a first capacitance connected between said input terminal and said first voltage supply terminal, a circuit node point, a second transistor connected between said circuit node point and said output terminal, said second transistor having a gate connected to said input terminal, a third transistor connected between said second voltage supply terminal and said circuit node point, said third transistor having a gate terminal for connection to a second control potential terminal, a fourth transistor connected between said second voltage supply terminal and said output terminal, said fourth transistor having its gate connected to said circuit node point, a second capacitance connected between said output terminal and said first voltage supply terminal, a third capacitance connected between said circuit node point and said first voltage supply terminal, a current sink connected between said output terminal and a third voltage supply terminal, said input terminal to said digital differential amplifier being connected to an output terminal of a first charge coupled device and said output terminal of said differential amplifier being connected to an input terminal of a second charge coupled device.

Claim 12

The combination according to claim 9, wherein the transistors of said digital differential amplifier are field effect transistors and are constructed by an aluminum-silicon-gate technique, and wherein said charge coupled devices are constructed by an aluminum-silicon-gate technique.

Claim 13

The method of operating the CCD detection system according to claim 7 where the process of selecting a data recirculation mode or data entry mode comprises applying a third control potential to said third control potential terminal and simultaneously applying a fourth control potential to said fourth control potential terminal such that said fifth transistor conducts only when said seventh transistor is not permitted to conduct and said fifth transistor is not permitted to conduct when said seventh transistor is permitted to conduct.

Claim 14

A CCD detection system comprising the combination of two digital differential amplifiers and two charge coupled devices for regenerating stored charges detected at the output of a first charge coupled device and transferring that regenerated charge to the input of a second charge coupled device or alternately, producing a data output signal proportional to the stored charge detected at the output of a first charge coupled device and generating a charge proportional to a data input signal at the input to a second charge coupled device comprising a digital differential amplifier which includes a first voltage supply terminal and a second voltage supply terminal, an input terminal, an output terminal, a first transistor connected to said input terminal via a first terminal of its source-drain-channel, said first transistor having a gate terminal for connection to a first control potential terminal, a first capacitance connected between said input terminal and said first voltage supply terminal, a circuit node point, a second transistor connected between said circuit node point and said output terminal, said second transistor having a gate connected to said input terminal, a third transistor connected between said second voltage supply terminal and said circuit node point, said third transistor having a gate terminal for connection to a second control potential terminal, a fourth transistor connected between said second voltage supply terminal and said output terminal, said fourth transistor having its gate connected to said circuit node point, a second capacitance connected between said output terminal and said first voltage supply terminal, a third capacitance connected between said circuit node point and said first voltage supply terminal, a current sink connected between said output terminal and a third voltage supply terminal, having said input terminal connected to an output terminal of a first charge coupled device, a second circuit node, a fifth transistor connected between said second circuit node and the input terminal of a second charge coupled device, said fifth transistor having its gate input connected to a third control potential terminal, a second digital differential amplifier having a sixth transistor connected between said amplifier input terminal and a data input terminal, said sixth transistor having its gate input connected to a data control potential terminal; a seventh transistor connected between said output terminal of said second digital differential amplifier and said input terminal to said second charge coupled device, said seventh transistor having its gate input connected to a fourth control potential terminal.

Claim 15

A CCD detection system comprising the combination of two digital differential amplifiers and two charge coupled devices for regenerating stored charges detected at the output of a first charge coupled device and transferring that regenerated charge to the input of a second charge coupled device or alternately, producing a data output signal proportional to the stored charge detected at the output of a first charge coupled device and generating a charge proportional to a data input signal at the input to a second charge coupled device comprising a digital differential amplifier which includes a first voltage supply terminal and a second voltage supply terminal, an input terminal, an output terminal, a first transistor connected to said input terminal via a first terminal of its source-drain-channel, said first transistor having a gate terminal for connection to a first control potential terminal, a first capacitance connected between said input terminal and said first voltage supply terminal, a circuit node point, a second transistor connected between said circuit node point and said output terminal, said second transistor having a gate connected to said input terminal, a third transistor connected between said second voltage supply terminal and said circuit node point, said third transistor having a gate terminal for connection to a second control potential terminal, a fourth transistor connected between said second voltage supply terminal and said output terminal, said fourth transistor having its gate connected to said circuit node point, a second capacitance connected between said output terminal and said first voltage supply terminal, a third capacitance connected between said circuit node point and said first voltage supply terminal, a current sink connected between said output terminal and a third voltage supply terminal, having said input terminal connected to an output terminal of a first charge coupled device, a second circuit node, a fifth transistor connected between said second circuit node and the input terminal of a second charge coupled device, said fifth transistor having its gate input connected to a third control potential terminal, a second digital differential amplifier having a sixth transistor connected between said amplifier input terminal and a data input terminal, said sixth transistor having its gate input connected to a data control potential terminal; a seventh transistor connected between said output terminal of said second digital differential amplifier and said input terminal to said second charge coupled device, said seventh transistor having its gate input connected to a fourth control potential terminal.

Claim 16

The combination according to claim 12, wherein the transistors of said digital differential amplifiers are field effect transistors and are constructed by an aluminum-silicon-gate technique and wherein said charge coupled devices are constructed by an aluminum-silicon-gate technique.

Claim 17

The combination according to claim 12, wherein said first capacitance comprises the capacitance of the diffusion zone of said first output terminal of said first charge coupled device; wherein said third capacitance comprises the parasitic capacitance of said second transistor, the parasitic capacitance of said third transistor and the capacitance of said gate input of said fourth transistor; wherein said second capacitance comprises the parasitic capacitance of said second transistor and of said fourth transistor.