Raised source and drain igfet device fabrication

Claim 2

A process for making an insulated gate field effect transistor device having shallow source and drain junctions, comprising the steps of: growing a first insulating layer of a first thickness on the surface of a silicon substrate of a first conductivity type; forming a first opening and a second opening spaced from said first opening in said insulating layer in the intended location for the source and drain respectively of the device; depositing a layer of silicon of a second conductivity type over the exposed surfaces of said insulating layer and said substrate; said silicon layer being formed in a polycrystalline phase in those regions lying over said insulating layer, with a first polysilicon region formed over the portion of said insulating layer between said first and said second opening and a second polysilicon region being formed over the portion of said insulating layer surrounding said first and said second openings; said silicon layer formed in an epitaxial monocrystalline phase in those regions lying over said exposed semiconductor substrate, with a first epitaxial region formed over said first opening and a second epitaxial region formed over said second opening; etching a first trough between said first polycrystalline silicon region and said first epitaxial silicon region and a second trough between said first polycrystalline silicon region and said second epitaxial silicon region; doping the surface of said substrate exposed by said first trough and said second trough with a dopant of said second conductivity type; growing a second insulating layer of a second thickness greater than said first thickness in said first and second troughs; forming electrical contacts with said first polycrystalline silicon region as a gate electrode, with said first epitaxial region as a source electrode, and with said second epitaxial region as a drain electrode; whereby an insulated gate field effect transistor device is formed in a process which decouples the fabrication of the source and drain P-N junctions from their conductivity interconnections.

Claim 3

The process of claim 1 wherein said step of growing the first insulating layer comprises thermally growing a silicon dioxide layer on said substrate.

Claim 4

The process of claim 1 wherein said step of doping comprises ion implanting the dopant in said substrate.

Claim 5

The process of claim 1 wherein said doping step comprises diffusing the dopant into said substrate.

Claim 6

The process of claim 1 which further comprises: following the step of depositing the layer of silicon, the steps of depositing a layer of silicon nitride over all exposed surfaces and patterning said silicon nitride layer by a first nitride etching step to form an etching mask for said first and said second troughs.

Claim 7

The process of claim 5 which further comprises: after the step of etching said first trough and said second trough, a second nitride etching step for etching said silicon nitride layer so as to remove said nitride layer from said second polycrystalline silicon region.

Claim 8

The process of claim 6 which further comprises: after said step of growing a second insulating layer, a third nitride etching step for etching said silicon nitride layer remaining on said first polycrystalline silicon region, said first epitaxial silicon region, and said second epitaxial silicon region; said second insulating layer being thermally grown silicon dioxide.

Claim 9

A process for fabricating an integrated circuit field effect transistor device having shallow source and drain regions, comprising the steps of: growing a silicon nitride layer on the surface of a silicon substrate; etching said silicon nitride layer so as to leave a first silicon nitride region and a second silicon nitride region spaced from said first silicon nitride region on the surface of said substrate; growing a first thermal oxide layer on the exposed portions of the surface of said silicon substrate so as to form a first thermal oxide region surrounding said first and second silicon nitride regions and a second thermal oxide region between said first and said second silicon nitride regions; etching said second thermal oxide region so as to expose the surface of said substrate beneath same; growing a second, thin thermal oxide layer between said first and said second silicon nitride regions; etching said first and said second silicon nitride regions so as to expose the surface of said silicon wafer thereunder as first and second window regions; depositing a silicon layer on all exposed surfaces; said silicon layer forming the polycrystalline silicon phase in those regions over said first thermal oxide layer and said thin thermal oxide layer; said silicon layer forming a first epitaxial monocrystalline region over said first window region exposing said silicon substrate and a second epitaxial monocrystalline region over said second window region exposing said silicon substrate; etching a first trough between said first epitaxial region and said thin oxide region and a second trough between said second epitaxial region and said thin oxide region; doping the surface of said substrate exposed by said first and second troughs with a dopant of said second conductivity type; growing a third thermal oxide layer thicker than said second thermal oxide layer, in said first and second troughs; forming an electrical contact with each polycrystalline silicon region; whereby an insulated gate field effect transistor is formed in a process which decouples the fabrication of the shallow source and drain junctions from their conductivity interconnections.

Claim 10

A process for fabricating an integrated circuit field effect transistor device having shallow source and drain regions, comprising the steps of: growing a silicon nitride layer on the surface of a silicon substrate; etching said silicon nitride layer so as to leave a first silicon nitride region and a second silicon nitride region spaced from said first silicon nitride region on the surface of said substrate; growing a first thermal oxide layer on the exposed portions of the surface of said silicon substrate so as to form a first thermal oxide region surrounding said first and second silicon nitride regions and a second thermal oxide region between said first and said second silicon nitride regions; etching said second thermal oxide region so as to expose the surface of said substrate beneath same; growing a second, thin thermal oxide layer between said first and said second silicon nitride regions; etching said first and said second silicon nitride regions so as to expose the surface of said silicon wafer thereunder as first and second window regions; depositing a silicon layer on all exposed surfaces; said silicon layer forming the polycrystalline silicon phase in those regions over said first thermal oxide layer and said thin thermal oxide layer; said silicon layer forming a first epitaxial monocrystalline region over said first window region exposing said silicon substrate and a second epitaxial monocrystalline region over said second window region exposing said silicon substrate; etching a first trough between said first epitaxial region and said thin oxide region and a second trough between said second epitaxial region and said thin oxide region; doping the surface of said substrate exposed by said first and second troughs with a dopant of said second conductivity type; growing a third thermal oxide layer thicker than said second thermal oxide layer, in said first and second troughs; forming an electrical contact with each polycrystalline silicon region; whereby an insulated gate field effect transistor is formed in a process which decouples the fabrication of the shallow source and drain junctions from their conductivity interconnections.