Patent US4049975A successfully refreshed from Google Patents.
US4049975A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor circuits
Assignee: Ferranti International PLC
•
Filing: 1976-12-21
•
Granted: 1977-09-20
•
Expires: 1996-12-21
Abstract
Abstract In a non-gold-doped TTL device to be energized by a potential supply of at least 4.5 volts; the charge carrier concentration within a NPN multi-emitter input transistor is reduced by connecting together the base and the collector; undesirable emitter-to-emitter transistor action is prevented, by reducing the inverse current gain factor of the input transistor, and preventing this transistor from saturating, by providing a diode within the phase splitter stage, to ensure that the input threshold level of the device is at least two forward biased diode potentials above the least positive supply rail; and providing a suitable pull-up stage for the output transistor, which pull-up stage may comprise a modified Darlington pair of transistors, including a resistor between the emitter of the first transistor and the base of the second transistor, and a resistor between the base and the emitter of the second transistor.
Inventors
- 👤 Stephen Francis Colaco
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10D62/17; H10D62/177
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
226 words
A transistor-transistor logic circuit arrangement having NPN transistors, and to be energised by a potential supply of at least 4.5 volts, including a multi-emitter input transistor, having an emitter individually connected to each required input for the circuit arrangement, the base is connected via a resistor to a first rail to be maintained at a first, finite positive potential level, the collector is connected to the base to reduce, in the operation of the circuit arrangement, the concentration of stored charge carriers within the transistor, and the collector is also connected to a phase splitter stage connected between the first rail and a second rail to be maintained at a second potential level, less positive than the potential level of the first rail, a diode is provided within the phase splitter stage, and is connected between the input transistor and the second rail to ensure that the input threshold level of the circuit arrangement is above the potential level of the second rail by substantially the maximum obtainable potential difference across two forward biased diodes, one output of the phase splitter stage is connected to the base of an output transistor for the circuit arrangement, the emitter of the output transistor is connected to the second rail, and the other output of the phase splitter stage is connected to a pull-up stage for the output transistor.
Claim 2
Dependent Claim
226 words
A transistor-transistor logic circuit arrangement having NPN transistors, and to be energised by a potential supply of at least 4.5 volts, including a multi-emitter input transistor, having an emitter individually connected to each required input for the circuit arrangement, the base is connected via a resistor to a first rail to be maintained at a first, finite positive potential level, the collector is connected to the base to reduce, in the operation of the circuit arrangement, the concentration of stored charge carriers within the transistor, and the collector is also connected to a phase splitter stage connected between the first rail and a second rail to be maintained at a second potential level, less positive than the potential level of the first rail, a diode is provided within the phase splitter stage, and is connected between the input transistor and the second rail to ensure that the input threshold level of the circuit arrangement is above the potential level of the second rail by substantially the maximum obtainable potential difference across two forward biased diodes, one output of the phase splitter stage is connected to the base of an output transistor for the circuit arrangement, the emitter of the output transistor is connected to the second rail, and the other output of the phase splitter stage is connected to a pull-up stage for the output transistor.
Claim 3
Dependent Claim
109 words
A circuit arrangement as claimed in claim 1 with the pull-up stage comprising a modified Darlington pair of transistors having a first transistor the base of which is connected to the associated output of the phase splitter stage, and a second transistor the emitter of which is connected to the collector of the output transistor, the collectors of both the first and second transistors are connected via a common resistor to the first rail, the emitter of the first transistor is connected via a resistor to the base of the second transistor, which base in turn is connected via a further resistor to the emitter of the second transistor.
Claim 4
Dependent Claim
239 words
A non-gold-doped transistor-transistor logic circuit device has at least partially embodied in a monolithic semiconductor body a circuit arrangement having NPN transistors, and to be energised by a potential supply of at least 4.5 volts, including a multi-emitter input transistor, having an emitter individually connected to each required input for the circuit arrangement, the base is connected via a resistor to a first rail to be maintained at a first, finite positive level, the collector is connected to the base to reduce, in the operation of the circuit arrangement, the concentration of stored charge carriers within the transistor, and the collector is also connected to a phase splitter stage connected between the first rail and a second rail to be maintained at a second potential level, less positive than the potential level of the first rail, a diode is provided within the phase splitter stage, and is connected between the input transistor and the second rail to ensure that the input threshold level of the circuit arrangement is above the potential level of the second rail by substantially the maximum obtainable potential difference across two forward biased diodes, one output of the phase splitter stage is connected to the base of an output transistor for the circuit arrangement, the emitter of the output transistor is connected to the second rail, and the other output of the phase splitter stage is connected to a pull-up stage for the output transistor.
Claim 5
Dependent Claim
239 words
A non-gold-doped transistor-transistor logic circuit device has at least partially embodied in a monolithic semiconductor body a circuit arrangement having NPN transistors, and to be energised by a potential supply of at least 4.5 volts, including a multi-emitter input transistor, having an emitter individually connected to each required input for the circuit arrangement, the base is connected via a resistor to a first rail to be maintained at a first, finite positive level, the collector is connected to the base to reduce, in the operation of the circuit arrangement, the concentration of stored charge carriers within the transistor, and the collector is also connected to a phase splitter stage connected between the first rail and a second rail to be maintained at a second potential level, less positive than the potential level of the first rail, a diode is provided within the phase splitter stage, and is connected between the input transistor and the second rail to ensure that the input threshold level of the circuit arrangement is above the potential level of the second rail by substantially the maximum obtainable potential difference across two forward biased diodes, one output of the phase splitter stage is connected to the base of an output transistor for the circuit arrangement, the emitter of the output transistor is connected to the second rail, and the other output of the phase splitter stage is connected to a pull-up stage for the output transistor.
Claim 6
Dependent Claim
108 words
A device as claimed in claim 3 with the pull-up stage comprising a modified Darlington pair of transistors having a first transistor the base of which is connected to the associated output of the phase splitter stage, and a second transistor the emitter of which is connected to the collector of the output transistor, the collectors of both the first and second transistors are connected via a common resistor to the first rail, the emitter of the first transistor is connected via a resistor to the base of the second transistor, which base in turn is connected via a further resistor to the emitter of the second transistor.
Claim 7
Dependent Claim
47 words
A device as claimed in claim 3 in which the semiconductor body comprises a thin epitaxial layer of P conductivity type on a substrate of the same conductivity type, and the base of each constituent transistor comprises at least partially an unmodified region of the epitaxial layer.
Claim 8
Dependent Claim
59 words
A device as claimed in claim 5 in which each constituent transistor has the so-called collector-diffusion-isolation construction, the N type collector of each transistor comprising both a buried layer at a portion of the interface between the epitaxial layer and the substrate and an isolation barrier for the transistor extending through the epitaxial layer to contact the buried layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-19 | 1981-03-21 | 1981-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-19 | 1985-03-21 | 1985-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-19 | 1989-03-21 | 1989-09-20 | $7700.00 | Window Closed / Lapsed |