Logic circuit using a current switch to compensate for signal deterioration

Claim 2

An improved logic circuit comprising: input semiconductive means for receiving an input signal, said input means having a base terminal, a collector terminal and an emitter terminal, output semiconductor means having a base terminal, a collector terminal and an emitter terminal, the output signal being taken from said emitter terminal, and current-switching means for compensating for signal deterioration in said logic circuit, said current-switching means including a first and a second current-switching semiconductive means each having a base terminal, a collector terminal and an emitter terminal, the base of said first current-switching semiconductive means being coupled to the base of said input semiconductive means and the collector of said second current-switching semiconductive means being coupled to the base of said output semiconductive means, said current-switching means further including unbalanced resistive means coupling the emitter of said first current-switching semiconductive means to the emitter of said second currentswitching semiconductive means for reducing the gain of said current-switching means, for linearizing the transfer characteristic of the logic circuit and for insuring unbalanced operation of said current-switching means thereby allowing said logic circuit to operate with relatively large signal swings.

Claim 3

The improved logic circuit of claim 1 wherein said unbalanced resistive means includes: a first resistive means coupled between the emitter of said first current-switching semiconductive means and the emitter of said second current-switching semiconductive means, second resistive means coupled between the emitter of said first current-switching semiconductive means and a source of negative potential, and third resistive means coupled between the emitter of said second current-switching semiconductive means and said source of negative potential.

Claim 4

The improved logic circuit of claim 2 further including emitter-follower means coupled between said input semiconductive means and said current-switching means for isolating the collector terminal of said input semiconductive means from the base-to-emitter capacitance of said input semiconductive means and improving the speed of operation of said logic circuit, said emitter-follower means including a transistor having its base coupled to the collector of said input semiconductor means and an emitter coupled between the base of said input semiconductive means and the base of said first current-switching semiconductive means.

Claim 5

The improved logic circuit of claim 3 further including output buffer means coupled between the emitter of said output semiconductive means and the output of the improved logic circuit for clamping the circuit output to a predetermined level offset from ground.

Claim 6

The improved logic circuit of claim 4 wherein said output buffer means includes an emitter-follower transistor having its base coupled to the emitter of said output semiconductive means, its collector coupled to a positive voltage source, and its emitter coupled to said circuit output and wherein said output buffer means further includes a clamping diode having its anode coupled to ground and its cathode coupled to the emitter of said emitter-follower transistor and wherein said output buffer means further includes a resistor coupled between the emitter of said emitter-follower transistor and the source of negative potential.

Claim 7

An improved logic circuit for providing a relatively large voltage swing and an approximately unity transfer characteristic between the input and output signals thereof comprising: a multiple emitter input transistor having a base electrode, a collector electrode and at least one emitter electrode for receiving input signals, an emitter-follower output transistor having a base electrode, a collector electrode, and an emitter electrode, said emitter electrode serving as a circuit output, and current-switching means serially coupled between the base of said multiple emitter input transistor and the base of said emitter-follower output transistor, said current-switching means including a first means responsive to the presence of an input signal indicative of a first logic state for defining a first current path and increasing the level of the output signal to a level indicative of said first logic state and to a value a predetermined amount greater than the value of said input signal, and said current-switching means further including a second means responsive to the presence of an input signal indicative of a second logic state for defining a Second current path and decreasing the level of said output signal to a level indicative of said second logic state and to a value a predetermined amount below the value of said input signal indicative of said second logic state.

Claim 8

An improved logic circuit for providing a relatively large voltage swing and an approximately unity transfer characteristic between the input and output signals thereof comprising: a multiple emitter input transistor having a base electrode, a collector electrode and at least one emitter electrode for receiving input signals, an emitter-follower output transistor having a base electrode, a collector electrode, and an emitter electrode, said emitter electrode serving as a circuit output, and current-switching means serially coupled between the base of said multiple emitter input transistor and the base of said emitter-follower output transistor, said current-switching means including a first means responsive to the presence of an input signal indicative of a first logic state for defining a first current path and increasing the level of the output signal to a level indicative of said first logic state and to a value a predetermined amount greater than the value of said input signal, and said current-switching means further including a second means responsive to the presence of an input signal indicative of a second logic state for defining a Second current path and decreasing the level of said output signal to a level indicative of said second logic state and to a value a predetermined amount below the value of said input signal indicative of said second logic state.

Claim 9

The logic circuit according to claim 6 wherein said current-switching means includes a current switch in series between the base of said multiple emitter transistor and the base of said emitter-follower output transistor, said current switching means including a first and second transistor and resistive means coupling the emitter of said first transistor with the emitter of said second transistor for creating an unbalanced amplifier stage.

Claim 10

The logic circuit according to claim 7 wherein the resistive means of said current-switching means further includes: a first resistor coupling the emitter of said first current-switching transistor to the emitter of said second current-switching transistor, a second resistor coupled between the emitter of said first current-switching transistor and a source of negative potential, and a third resistor unequal to said second resistor for coupling the emitter of said second current-switching transistor to said source of negative potential.

Claim 11

The logic circuit of claim 7 further including: means for clamping the circuit output, and means coupled between the collector of said multi-emitter input transistor and the base of said first current-switching transistor for improving the speed of operation of said logic circuit.

Claim 12

The logic circuit of claim 9 wherein said means for improving the speed of the logic circuit includes; an emitter-follower transistor having its base coupled to the collector of said multi-emitter input transistor and its emitter coupled to the base of said first current-switching transistor for isolating the collector of said multi-emitter input transistor from the base-to-emitter capacitance of said multiple emitter input transistor and a resistor coupled between the base of said first current-switching transistor and a source of negative potential, and wherein said clamping means includes; A second emitter-follower output transistor having its base coupled to the output of said first emitter-follower output transistor, its collector coupled to a source of positive potential and its emitter coupled to said circuit output, a diode having its cathode coupled to the emitter of said second emitter-follower transistor and its anode coupled to ground, and resistive means coupled between the emitter of said second emitter-follower transistor and said source of negative potential.