Digital converter from continuous variable slope delta modulation to pulse code modulation

Claim 2

A digital converter for converting a delta modulation signal being at a delta rate into a pulse code modulation (PCM) signal flowing at a PCM rate, comprising (a) a first conversion means receiving said delta signal for converting the code of said delta signal into an intermediate code, the signal of said intermediate code being at a rate corresponding to said delta rate; (b) a second conversion means connected to said first conversion means for converting the rate of said intermediate code signal into the rate of said PCM signal; (c) a third conversion means fed with said intermediate code signal at said PCM rate for converting said intermediate code into the code of said PCM signal, said third conversion means comprising a pulse code modulation compressor.

Claim 3

A digital converter as claimed in claim 1, wherein the intermediate code signal is a linear pulse code modulation signal.

Claim 4

A digital converter as claimed in claim 1, wherein said first conversion means includes a gain control circuit connected to a digital integration circuit for digitally integrating all binary numbers received from the digital control circuit and for producing once per delta sampling period a binary number which represents the sum of all delta steps, and a low-pass digital filter receiving said binary number for attenuating the high frequencies of said binary number, whereby said linear pulse code modulation signal at the delta rate is obtained.

Claim 5

A digital converter as claimed in claim 3, wherein said gain control circuit includes a digital control circuit receiving said delta signal, a digital low pass syllabic filter connected to the output of said digital control circuit, and a multiplier for weighting the input delta signal with the output of said syllabic filter.

Claim 6

A digital converter as claimed in claim 4, wherein the digital control circuit is controlled by a three-bit memory.

Claim 7

A digital converter as claimed in claim 3, wherein the digital integration circuit is a logic circuit which reconstructs the amplitude of the information contained in the delta signal.

Claim 8

A digital converter as claimed in claim 2, wherein said second conversion means include a holder for storing the linear pulse code modulation signal during a time equal to one delta sampling period, a first sampler connected to said holder for sampling the linear pulse code modulation signal at a predetermined sampling rate, a low-pass filter connected to said first sampler for filtering quantizing and out-of-band noises, and a second sampler for sampling the output of the low-pass filter at the pulse code modulation rate.

Claim 9

A digital converter as claimed in claim 7, wherein a clock control circuit is provided for synchronizing the signal holding time of said holder to the sampling rate of said first sampler, said control circuit including a flip-flop circuit simultaneously receiving a signal at said first sampler rate and another signal at said delta rate, an OR gate for adding said signal at the first sampler rate to an output of said flip-flop circuit, the output of said gate being applied to said first sampler while said another signal is applied to said holder.

Claim 10

A digital converter as claimed in claim 8, wherein said clock control circuit further includes a first delay circuit inserted before said gate and a second delay circuit inserted before said holder, said first delay circuit having a time delay which is half of the time delay of said second circuit.

Claim 11

A digital converter for converting a delta modulation signal being at a delta rate into a pulse code modulation (PCM) signal flowing at a PCM rate, comprising (a) a code conversion means including a digital integration circuit receiving said delta signal for digitally integrating all binary numbers thereof and for producing once per delta sampling period a binary number which represents the sum of all delta steps, and a low-pass digital filter receiving said binary number for attenuating the high frequencies of said binary number, whereby the code of said delta signal is converted into an intermediate code, the signal of said intermediate code being a linear PCM signal flowing at said delta rate; (b) a rate conversion means including a holder for storing said linear PCM signal during a time equal to one delta sampling period, a first sampler connected to said holder for sampling the linear PCM signal at a predetermined sampling rate, a low-pass filter connected to said first sampler for filtering quantizing and out-of-band noises, and a second sampler for sampling the output of the low-pass filter at said PCM rate, whereby the rate of said linear PCM signal is converted into the rate of said PCM signal; (c) a pulse code modulation compresser receiving said linear PCM signal at the PCM rate for converting the code of said linear signal into the code of said PCM signal; whereby the code and the rate of said delta modulation signal is converted into the code and the rate of said PCM signal.

Claim 12

A digital converter for converting a delta modulation signal being at a delta rate into a pulse code modulation (PCM) signal flowing at a PCM rate, comprising (a) a code conversion means including a digital integration circuit receiving said delta signal for digitally integrating all binary numbers thereof and for producing once per delta sampling period a binary number which represents the sum of all delta steps, and a low-pass digital filter receiving said binary number for attenuating the high frequencies of said binary number, whereby the code of said delta signal is converted into an intermediate code, the signal of said intermediate code being a linear PCM signal flowing at said delta rate; (b) a rate conversion means including a holder for storing said linear PCM signal during a time equal to one delta sampling period, a first sampler connected to said holder for sampling the linear PCM signal at a predetermined sampling rate, a low-pass filter connected to said first sampler for filtering quantizing and out-of-band noises, and a second sampler for sampling the output of the low-pass filter at said PCM rate, whereby the rate of said linear PCM signal is converted into the rate of said PCM signal; (c) a pulse code modulation compresser receiving said linear PCM signal at the PCM rate for converting the code of said linear signal into the code of said PCM signal; whereby the code and the rate of said delta modulation signal is converted into the code and the rate of said PCM signal.