US3707712A
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Converter from delta modulation to pulse code modulation
Assignee: Université de Sherbrooke
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Filing: 1970-06-10
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Granted: 1972-12-26
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Expires: 1990-06-10
Abstract
Abstract A system for the conversion of a delta modulation ( Delta M) signal into a pulse code modulation (PCM) signal and vice versa. The system for the conversion of a Delta M modulation signal into a PCM modulation signal comprises: register means for storing an input signal consisting of n binary digits generated by a Delta M modulator during a time period corresponding to a normal PCM modulation sampling period Ti, each binary digit representing a positive or negative Delta M modulation quantization step of a quantized signal; means for effecting the algebraic sum of the positive and negative quantization steps to obtain the increase or decrease of the quantized signal during the sampling period; means for multiplying the algebraic sum by a constant K representing the ratio of the value of a Delta M modulation quantization step over the value of a PCM modulation quantization step to obtain a binary signal representing the increase or decrease of the quantized signal in pulse code modulation quantization steps; and means for adding the binary signal obtained by the above multiplication to the binary signal obtained during the sampling period Ti 1 to obtain a binary output signal corresponding to the required pulse code modulation signal.
Inventors
- 👤 Pierre A Deschenes
- 👤 Michel Villeret
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:33
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/3002; H03M7/3048
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
232 words
A system for the conversion of a delta modulation signal generated by a delta modulator into a pulse code modulation signal comprising: a. register means for stOring an input signal consisting of a number n of binary digits generated by said delta modulator during a time period corresponding to a normal pulse code modulation sampling period Ti, said number n being greater than zero and each binary digit representing a positive or negative delta modulation quantization step of a quantized signal; b. means for effecting the algebraic sum of said positive and negative quantization steps to obtain the increase or decrease of the quantized signal during said sampling period; c. means for multiplying said algebraic sum by a constant positive integer K representing the ration of the value of a delta modulation quantization step over the value of a pulse code modulation quantization step to obtain a binary signal representing said increase or decrease of the quantized signal in pulse code modulation quantization steps; d. means for adding the binary signal obtained by said multiplication to the binary signal obtained during the preceding sampling period Ti 1 to obtain a m bit binary output signal corresponding to the regular pulse code modulation signal; and e. a digital compressor for receiving said output signal for transforming said output signal to a q bit pulse code modulation signal, where q is less than m.
Claim 2
Independent Claim
232 words
A system for the conversion of a delta modulation signal generated by a delta modulator into a pulse code modulation signal comprising: a. register means for stOring an input signal consisting of a number n of binary digits generated by said delta modulator during a time period corresponding to a normal pulse code modulation sampling period Ti, said number n being greater than zero and each binary digit representing a positive or negative delta modulation quantization step of a quantized signal; b. means for effecting the algebraic sum of said positive and negative quantization steps to obtain the increase or decrease of the quantized signal during said sampling period; c. means for multiplying said algebraic sum by a constant positive integer K representing the ration of the value of a delta modulation quantization step over the value of a pulse code modulation quantization step to obtain a binary signal representing said increase or decrease of the quantized signal in pulse code modulation quantization steps; d. means for adding the binary signal obtained by said multiplication to the binary signal obtained during the preceding sampling period Ti 1 to obtain a m bit binary output signal corresponding to the regular pulse code modulation signal; and e. a digital compressor for receiving said output signal for transforming said output signal to a q bit pulse code modulation signal, where q is less than m.
Claim 3
Dependent Claim
63 words
A system as defined in claim 1, wherein elements b), c) and d) are combined in ''''a digital integrator'''' including a reversible binary counter capable of storing said binary output signal, said reversible counter being fed with an input signal corresponding to K positive or K negative pulses representing the increase or decrease of the quantized signal in pulse code modulation quantization steps.
Claim 4
Dependent Claim
124 words
A system as defined in claim 2, wherein the maximum number of Delta M quantization steps of the quantized input signal is 23 and may be represented by a three binary digit number plus a fourth digit for the sign, and wherein K is equal to 27, whereby said binary output signal is a number comprising ten binary digits representing the amplitude of the quantized signal and an 11th digit representing the sign of the quantized signal and in which the seven less significant digits are null, and wherein said reversible binary counter comprises three binary storage elements capable of storing the absolute value of the three most significant digits of said output signal and an additional storage element for storing the sign thereof.
Claim 5
Dependent Claim
102 words
A system as defined in claim 3, wherein said ''''digital integrator'''' comprises a first gate circuit responsive to the sign of said input signal and to the output signal stored in said reversible counter for detecting a change of sign of the output signal stored in the binary reversible counter and for storing said change of sign in said additional storage element, and a second gate circuit responsive to both said additional storage element and to the sign of the input signal to be stored in said reversible counter for causing the level of said reversible counter to rise or fall accordingly.
Claim 6
Dependent Claim
108 words
A system as defined in claim 3, further comprising circuit means for transforming the number having three significant binary digits stored in the storage elements of said reversible counter and representing the amplitude of the output signal, and the additional binary digit stored in said additional storage element of said reversible counter and representing the sign of the amplitude of said output signal into a number having six binary digits representing the amplitude of the output signal and a seventh binary digit representing the sign of the amplitude of the output signal to produce a seven binary digit number corresponding to the normal pulse code modulation code number.
Claim 7
Dependent Claim
129 words
A system as defined in claim 5, wherein said transforming means comprises an output register having storage elements for storing said six binary digit number representing the amplitude Of the output signal, a first gate circuit responsive to predetermined combinations of binary digits in the storage elements of said reversible counter for identifying the group to which said binary digit number belongs and for storing the digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said binary reversible counter to predetermined storage elements of said output register and responsive to said first gate circuit for transferring the binary digits relating to the level of said binary digit number into the predetermined storage elements of said output register.
Claim 8
Dependent Claim
142 words
A system as defined in claim 1, for use with a delta modulator of the double integration type wherein the maximum number of consecutive positive or negative pulses of said input signal is eight, wherein the maximum number of Delta M quantization steps is 25, and wherein K equals 25 thus rendering the five less significant digits of the binary output signal null, said elements b), c) and d) being combined in a ''''digital integrator'''' comprising a first stage of integration including a first reversible counter capable of storing said maximum number of consecutive positive or negative pulses and a second stage of integration including a second reversible counter capable of storing the five most significant binary digits of the output signal, and a linking circuit for transferring the binary digits stored into the first integration stage into the second integration stage.
Claim 9
Dependent Claim
57 words
A system as defined in claim 7, wherein said linking circuit comprises an auxiliary counter, a comparator to which is applied the output of said first integration stage and the output of said auxiliary counter, and a pulse generator responsive to the output of said comparator for storing the required binary digits into said second integration stage.
Claim 10
Dependent Claim
90 words
A system as defined in claim 7, further comprising circuit means for transforming said number having five significant binary digits stored into the five storage elements of said second reversible counter and representing the amplitude of the output signal and an additional binary digit representing the sign of the amplitude into a number having six binary digit representing the amplitude of the output signal and a seventh binary digit representing the sign of the amplitude to produce a seven binary digit number corresponding to the normal pulse code modulation code.
Claim 11
Dependent Claim
121 words
A system as defined in claim 9, wherein said transforming means comprises an output register having six storage elements for storing the amplitude of the signal, a first gate circuit responsive to predetermined combinations of binary digits in the storage elements of said second binary counter for identifying the group to which said five binary digits belong and for storing the digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said second reversible counter to said output register and responsive to said first gate circuit for transferring the binary digits relating to the level of said five binary digit number into the predetermined storage elements of said output register.
References Cited (Backward Citations)
US3145292A
Cited
US3296612A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-26 | 1976-06-26 | 1976-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-26 | 1980-06-26 | 1980-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-26 | 1984-06-26 | 1984-12-26 | $7700.00 | Window Closed / Lapsed |