Code conversion apparatus

Claim 2

A code conversion apparatus comprising: an input terminal to which a first code signal is supplied; a digital bilateral integrating circuit provided with an increasing signal input connected to said input terminal and a decreasing signal input; a signal discriminating circuit for judging whether the content of said digital bilateral integrating circuit exceeds a predetermined value and for producing a second code signal in response to the judged results; a pulse generator adapted to receive said second code signal as input thereof for generating pulse signals groups of which have a predetermined relationship with the sequence of said second code signal, the clock rate of the pulses of said groups being sufficiently greater than the clock rate of said first code signal so that each group of pulse signals is generated over a time interval equal to or less than the clock period of said first code signal; and meAns for feeding back said groups of pulse signals to said decreasing signal input, whereby said second code signal from which a decoded signal substantially equal to the decoded signal from said first code signal is obtained and which has lower clock rate than that of said first code signal is produced at output side of said signal discriminating circuit.

Claim 3

A code conversion system for converting a predictable type first pulse code, each code pulse representing the polarity of a first predetermined magnitude step increment, to a predictable type second code, at a lower clock rate than the clock rate of said first code, each code pulse of said second code representing the polarity of a second predetermined magnitude step increment, comprising: a digital bilateral integrating circuit receiving said first code at an increasing signal input thereof and including a decreasing signal input, discriminating circuit means for judging if the content of said integrating circuit equals or exceeds a predetermined value and for generating said second code in response to the judging results, pulse generator means, responsive to said second code, for generating groups of pulses, the number of pulses in each group being equal in number to the ratio of said second predetermined magnitude to said first predetermined magnitude, and means for applying said groups of pulses to said decreasing signal input.

Claim 4

A code conversion system for converting a predictable type first pulse code, each code pulse representing the polarity of a first predetermined magnitude step increment, to a predictable type second code, at a lower clock rate than the clock rate of said first code, each code pulse of said second code representing the polarity of a second predetermined magnitude step increment, comprising: a digital bilateral integrating circuit receiving said first code at an increasing signal input thereof and including a decreasing signal input, discriminating circuit means for judging if the content of said integrating circuit equals or exceeds a predetermined value and for generating said second code in response to the judging results, pulse generator means, responsive to said second code, for generating groups of pulses, the number of pulses in each group being equal in number to the ratio of said second predetermined magnitude to said first predetermined magnitude, and means for applying said groups of pulses to said decreasing signal input.

Claim 5

The system of claim 2 wherein said pulse generator means comprises: coincidence gate means, timing circuit means coupled to said gate means and responsive to said second code for enabling said gate means for a preselected time, and clock means coupled to said coincidence gate means, for generating clock pulses at a repetition rate determined by said ratio.

Claim 6

A code conversion system for converting a predictable type first pulse code, each code pulse representing the polarity of a first predetermined magnitude step increment, to a lower clock rate, predictable type second pulse code, each second code pulse representing the polarity of one of multiple possible step increments of different magnitudes, the magnitude of the step increments being determined in response to the relation between foregoing successive code pulses of said second code, comprising: a digital bilateral integrating circuit receiving said first code at an increasing signal input thereof and including a decreasing signal input; discriminating circuit means for judging if the contents of said integrating circuit equals or exceeds a predetermined value and for generating said second code in response to the judging results, pulse generator means responsive to said second code, for generating pulse groups of varying numbers of pulses in response to the relationship between the values of foregoing successive pulses of said second code, the clock rate of the pulses of said pulse groups being at a rate sufficiently greater than the clock rate of said first pulse code so that each pulse group is generated over a time interval equal to or less than the clock period of said first pulse code and means for applying said pulse groups to said decreasing signal input.

Claim 7

A code conversion system for converting a predictable type first pulse code, each code pulse representing the polarity of a first predetermined magnitude step increment, to a lower clock rate, predictable type second pulse code, each second code pulse representing the polarity of one of multiple possible step increments of different magnitudes, the magnitude of the step increments being determined in response to the relation between foregoing successive code pulses of said second code, comprising: a digital bilateral integrating circuit receiving said first code at an increasing signal input thereof and including a decreasing signal input; discriminating circuit means for judging if the contents of said integrating circuit equals or exceeds a predetermined value and for generating said second code in response to the judging results, pulse generator means responsive to said second code, for generating pulse groups of varying numbers of pulses in response to the relationship between the values of foregoing successive pulses of said second code, the clock rate of the pulses of said pulse groups being at a rate sufficiently greater than the clock rate of said first pulse code so that each pulse group is generated over a time interval equal to or less than the clock period of said first pulse code and means for applying said pulse groups to said decreasing signal input.

Claim 8

The code conversion system of claim 4 wherein said pulse generator means comprises: means for producing signals representative of the relationship between two successive pulses of said second code, counter means, incremented in response to two successive identical pulses of said second code and reset in response to a loss of correspondence between successive pulses of said second code, and a pulse generating circuit, responsive to the counter means and said second code for generating pulse groups comprised of different numbers of pulses.

Claim 9

The code conversion system of claim 5 wherein said counter means includes means, responsive to a predetermined count, for blocking the further incrementing of said counter means.

Claim 10

The code conversion system of claim 6 wherein said pulse generating circuit comprises: first and second control inputs, responsive to different counts in said counter means, a second code signal input, clock means for generating clock pulses at a substantially greater rate than the clock rate of said first code, and logic means for applying selected numbers of said clock pulses to said decreasing signal input in response to the signals on said first and second control inputs and second code signal input.

Claim 11

The code converter system of claim 7 wherein said logic means comprises: shift register means, periodically preset at intervals corresponding to the frequency clock rate of said second code and responsive to said clock pulses for shifting the preset contents, first coincidence gate means, a first input thereof being coupled to said first control input, a second input being coupled to selected stages of said shift register, second coincidence gate means, a first input thereof being coupled to said second control input, a second input being coupled to selected stages of said shift register, exclusive OR gate means coupled to said second code signal input and the outputs of said first and second coincidence gates, and third coincidence gate means, coupled to the output of said exclusive OR gate and said clock means, whereby the output of said exclusive OR gate enables the passing of selected numbers of clock pulses to said decreasing signal input.

Claim 12

The code conversion system of claim 8 wherein said pulse generating circuit further includes, means responsive to a predetermined state of said shift register for blocking the further shifting of the contents thereof until the next succeeding preset time.