Speed-tolerant digital decoding system

Claim 1

A pulse-width signal-decoding system into which a signal passes, said signal comprising a plurality of adjacent cells, each defined at the ends by a rapid transition of a signal amplitude in a first direction and at some intermediate point by a rapid transition of the signal amplitude in a second and opposite direction, comprising: (a) data-detecting means for examining each cell to produce a logical "1" or a logical "0", depending only on whether said intermediate point occurs in one or the other half width between said ends of each cell; (b) sync-cell detector means for examining each cell to detect the presence of a sync cell (defined as being of at least approximately double normal cell width) and producing an unloading pulse therefrom; (c) shift register means coupled to said data-detecting means for temporary separate adjacent storage of the adjacent data bits comprising said logical "1"s and said logical "0"s detected by said data-detecting means; (d) a buffer register coupled to said shift register; and (e) means responsive to said unloading pulse from said sync-cell detector, at the occurrence of a sync cell, to load said shift register into said buffer register: wherein said data-detecting means comprises: (a) up-down counter means having an up input, a down input, an output indicating the sign of the count, and a reset terminal; (b) an oscillator; (c) a signal input line; (d) a first AND gate with output connected to said up input, one input connected to said oscillator, and the second input connected to said signal input line; (e) a second AND gate and an inverter, said second AND gate with output connected to said down input, one input connected to said oscillator, and the second input connected through said inverter to said signal input line; (f) said output of said up-down counter connected to said shift register means; and (g) cell-detector means connected to said input signal line for producing a cell edge signal at the start of each cell, the output of said cell detector being connected to said reset terminal of said up-down counter and to a shift input of said shift register: and wherein said sync-cell detector means comprises: (a) a cell-width counter having an input terminal connected to said oscillator, a reset terminal connected to said cell detector means, and a plurality of output leads for representing the count as a multibit binary number; (b) a binary adder means having a first plurality of input terminals, a second plurality of input terminals, and a plurality of output terminals, said first input terminals connected systematically to the corresponding output of said cell-width counter, said second inputs being systematically connected to said first inputs at terminals, each one less than the corresponding said first plurality of terminals, in a way to represent a binary number of one-half the value of the number on said first input terminals, whereby the signal on said output terminals represents 1.5 times that on said output leads of said cell-width counter; (c) a preset downcounter having a plurality of input leads, connected systematically to the corresponding said plurality of output leads of said adder means and a down count input connected to said oscillator; (d) means connected to said downcounter and to the cell detector means to preset it to the number represented by said adder output at the occurrence of a cell edge signal; and (e) output means connected to said downcounter to indicate when its said count is 0, said count of 0 being an indication of detection of a sync cell.