US3823397A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial to parallel converter for binary signals of two different pulse widths
Assignee: Genicom Corp
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Filing: 1972-07-14
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Granted: 1974-07-09
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Expires: 1992-07-14
Abstract
Abstract A high-speed printer of the dot matrix type in which incoming information to be printed, presented in either serial or parallel form, is examined for invalid bits and loaded into a buffer in parallel fashion. Printing does not begin until the buffer is loaded to print a line of the desired length. Printing begins as soon as the first character loaded into the buffer reaches the output stage at which time the actuation of the print wires of the dot matrix are moved across the paper document at a substantially constant speed. Detection of the location of the carriage assembly moving the printer head assembly is performed independent of the movement of the carriage to actuate the print wires at the appropriate locations. Logical circuitry is provided for detecting the presence of invalid characters and the buffer and serial-to-parallel converter are cleared prior to the loading of the next group of characters to be printed on the next line of print. During serial transmission, the printer assembly generates Acknowledge signals to indicate to the transmitting facility that the previous character has been received and stored.
Inventors
- 👤 H Menhennett
- 👤 R Howard
- 👤 P Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:33
CPC Classifications
B; B41; B41J; B41J2/00; B41J2/22; B41J2/23; B41J2/27; B41J2/285; B41J2/235; B41J2/265; G; G06; G06K; G06K15/00; G06K15/02; G06K15/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
222 words
A serial to parallel converter for converting incoming binary data signals presentqd in serial fashion into parallel data for loading into a multistage buffer wherein all bits are of equal time duration, and wherein binary states of the bits all undergo the same abrupt signal level transition upon their initiation and wherein a first portion of a bit of a first binary state is greater in length than the first portion of a bit of the opposite binary state comprising: an input line for receiving serially transmitted data signals; a multistage shift register having an input directly coupled to said input line for receiving and temporarily storing a group of bits; timing means including a couNter coupled to said input line for beginning a count upon the initiation of each and every bit; means coupled to said timing means for initiating the loading of each bit into said register; said loading initiating means comprising means for generating a loading pulse when said timing means achieves a predetermined count, said count occurring after the first portion of a bit of said opposite state and before the first portion of a bit of said first binary state; said register including means responsive to said loading pulse for inserting the binary state of the bit in the input line at such time into said register.
Claim 2
Dependent Claim
222 words
A serial to parallel converter for converting incoming binary data signals presentqd in serial fashion into parallel data for loading into a multistage buffer wherein all bits are of equal time duration, and wherein binary states of the bits all undergo the same abrupt signal level transition upon their initiation and wherein a first portion of a bit of a first binary state is greater in length than the first portion of a bit of the opposite binary state comprising: an input line for receiving serially transmitted data signals; a multistage shift register having an input directly coupled to said input line for receiving and temporarily storing a group of bits; timing means including a couNter coupled to said input line for beginning a count upon the initiation of each and every bit; means coupled to said timing means for initiating the loading of each bit into said register; said loading initiating means comprising means for generating a loading pulse when said timing means achieves a predetermined count, said count occurring after the first portion of a bit of said opposite state and before the first portion of a bit of said first binary state; said register including means responsive to said loading pulse for inserting the binary state of the bit in the input line at such time into said register.
Claim 3
Dependent Claim
126 words
The converter of claim 1 further comprising buffer means for receiving the parallel output of said register; said bits being transmitted in groups to represent a particular character, each of said groups being followed by a constant level stop pulse of a duration greater than said bits; means coupled between said timing means and said input line for resetting said timing means upon the initiation of each bit in said input line; means coupled to said timing means for generating a clear signal when said timing means generates a second predetermined count which is greater than said first predetermined count; said register including clearing means responsive to said clear signal generating means for clearing the contents of said register in the presence of a clear signal.
Claim 4
Dependent Claim
58 words
The converter of claim 2 further comprising shift means for shifting the contents of said converter into said buffer; each of said groups of bits being preceded by a start signal of a predetermined binary state; means being coupled between said shift means and the stage of said register containing said start signal for energizing said shift means.
Claim 5
Dependent Claim
87 words
The circuitry of claim 1 further comprising second timing means coupled to said input line being initiated by the start of each bit to generate a second timing signal a predetermined time period longer than the interval of a bit, said second timing means adapted to be reset upon the initiation of each newly received bit to begin a new cycle before generating said second timing signal; means coupled to said second timing means to clear said register means only upon receipt of a second timing signal.
Claim 6
Dependent Claim
54 words
The circuitry of claim 4 wherein said clearing means further comprises means coupled to the last stage of the first register means and said second timing means for clearing said first register means when a bit has not been shifted to said last stage at the time that said second timing signal is generated.
Claim 7
Dependent Claim
77 words
The circuit of claim 5 further comprising second register means having its inputs coupled in parallel to the outputs of said first register means; said clearing means being coupled to said second register means to enable the contents of said first register means to be transferred in parallel fashion to said second register means only when a bit has been shifted into the last stage of said first register means and said second timing signal is generated.
References Cited (Backward Citations)
US3201759A
Cited
US3313922A
Cited
US3416133A
Cited
US3310626A
Cited
US3160876A
Cited
US3395400A
Cited
US3508228A
Cited
US3546592A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-08 | 1978-01-07 | 1978-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-08 | 1982-01-07 | 1982-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-08 | 1986-01-07 | 1986-07-09 | $7700.00 | Window Closed / Lapsed |