US3887769A
Expired / Lapsed
US
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Frame syncrhonization of elastic data bit stores
Assignee: AT&T Inc
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Filing: 1973-04-04
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Granted: 1975-06-03
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Expires: 1993-04-04
Abstract
Abstract Shift register stages delay incoming frames of data to align each frame with framing pulses of a local clock and to compensate for jitter of the incoming data stream. Variable delay is provided by a counter whose count defines the register output stage. Framing synchronization is initially obtained, or regained where lost, by first determining when the framing signal shifts to the output stage, then advancing the count at the incoming bit rate to define each successive stage when the framing signal shifts thereto and halting the advance when the local framing pulse is generated. If the count advances to define a final one of the register stages, the count is reduced by a number equal to the number of bits in a frame. If the count is decreased to define an initial stage, the count is increased by this same number.
Inventors
- 👤 Jr Michael Peter Cichetti
- 👤 Robert Jeffrey Fretz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:23
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
135 words
An elastic store for receiving incoming frames of serial data, each frame having a fixed number of bits and including at least one framing bit for defining the demarcation between successive incoming frames, comprising, variable delay means for delaying the bits and thereby producing bits delayed a predetermined interval of time; a local clock for generating framing pulses; means for detecting the misalignment in time of the delayed framing bit and the generated framing pulse; and means operated in response to the detecting means for cumulatively increasing the delay of the delay means by an interval of time equal to the interval that the increasing means is operating, said increasing means commencing operation at the time that the delayed framing bit is produced and concluding operation at the time that the framing pulse is generated.
Claim 2
Dependent Claim
135 words
An elastic store for receiving incoming frames of serial data, each frame having a fixed number of bits and including at least one framing bit for defining the demarcation between successive incoming frames, comprising, variable delay means for delaying the bits and thereby producing bits delayed a predetermined interval of time; a local clock for generating framing pulses; means for detecting the misalignment in time of the delayed framing bit and the generated framing pulse; and means operated in response to the detecting means for cumulatively increasing the delay of the delay means by an interval of time equal to the interval that the increasing means is operating, said increasing means commencing operation at the time that the delayed framing bit is produced and concluding operation at the time that the framing pulse is generated.
Claim 3
Dependent Claim
135 words
An elastic store for receiving incoming frames of serial data, each frame having a fixed number of bits and including at least one framing bit for defining the demarcation between successive incoming frames, comprising, variable delay means for delaying the bits and thereby producing bits delayed a predetermined interval of time; a local clock for generating framing pulses; means for detecting the misalignment in time of the delayed framing bit and the generated framing pulse; and means operated in response to the detecting means for cumulatively increasing the delay of the delay means by an interval of time equal to the interval that the increasing means is operating, said increasing means commencing operation at the time that the delayed framing bit is produced and concluding operation at the time that the framing pulse is generated.
Claim 4
Dependent Claim
135 words
An elastic store for receiving incoming frames of serial data, each frame having a fixed number of bits and including at least one framing bit for defining the demarcation between successive incoming frames, comprising, variable delay means for delaying the bits and thereby producing bits delayed a predetermined interval of time; a local clock for generating framing pulses; means for detecting the misalignment in time of the delayed framing bit and the generated framing pulse; and means operated in response to the detecting means for cumulatively increasing the delay of the delay means by an interval of time equal to the interval that the increasing means is operating, said increasing means commencing operation at the time that the delayed framing bit is produced and concluding operation at the time that the framing pulse is generated.
Claim 5
Dependent Claim
45 words
An elastic store in accordance with claim 1, including means responsive to the extension of the delay interval to a selected maximum interval of time for reducing the delay interval by an interval of time corresponding to the time occupied by one frame of data.
Claim 6
Dependent Claim
141 words
An elastic store for receiving incoming frames of serial data, each frame having a fixed number of bits and including at least one framing bit for defining the demarcation between successive incoming frames, comprising, a multistage data bit register; a local clock for generating framing pulses; means for inserting the incoming serial bits into the multistage register; means for reading successive ones of the inserted bits out of selected stages of the multistage register on a first in-first out basis; and means responsive to misalignment in time of the read out framing bit and the framing pulse for selectively shifting the reading means to progressively higher stages of the register concurrently with the shifting of the framing bit thereto for the interval from the time that the framing bit is read out to the time that the framing pulse is generated.
Claim 7
Dependent Claim
141 words
An elastic store for receiving incoming frames of serial data, each frame having a fixed number of bits and including at least one framing bit for defining the demarcation between successive incoming frames, comprising, a multistage data bit register; a local clock for generating framing pulses; means for inserting the incoming serial bits into the multistage register; means for reading successive ones of the inserted bits out of selected stages of the multistage register on a first in-first out basis; and means responsive to misalignment in time of the read out framing bit and the framing pulse for selectively shifting the reading means to progressively higher stages of the register concurrently with the shifting of the framing bit thereto for the interval from the time that the framing bit is read out to the time that the framing pulse is generated.
Claim 8
Dependent Claim
30 words
An elastic store in accordance with claim 3, wherein the shifting means includes means for operating the reading means to repeatedly read the framing bit out of the multistage register.
Claim 9
Dependent Claim
145 words
An elastic store in accordance with claim 4, wherein the data bit register comprises a multistage shift register, the inserting means inserts the incoming bits into an initial one of the stages of the register, the reading means reads the inserted bits out of a selected one of the subsequent stages, the reading means including, counting means for advancing up a count when the inserted bits exceed in number the read out bits and for advancing down the count when the read out bits exceed In number the inserted bits, and means responsive to each of the counter counts for selecting individual ones of the subsequent stages; and the shifting means includes means for advancing up the count of the counting means in response to each insertion of an incoming bit, whereby successive stages are selected concurrent with the shifting of the framing bit thereto.
Claim 10
Dependent Claim
58 words
An elastic store in accordance with claim 3 and further including means responsive to the advance of the count to a predetermined number for resetting the counter to a lesser count differing from the predetermined number by the fixed number, whereby one frame of data is discarded and the framing bit of the next frame is read out.
Claim 11
Dependent Claim
198 words
An elastic store for receiving frames of data, each frame consisting of a fixed number of data bits, comprising, a multistage data bit register having a storage capacity of at least one frame of data, each stage of the data bit register for storing a data bit; means for inserting the received data bits into the register at a rate controlled by the rate of the received data bits; means for reading the inserted data bits out of selected stages of the register at a rate controlled by a local clock, on a first in-first out basis; means jointly responsive to the inserting means and the reading means for determining a filling of the register with inserted bits awaiting readout; and means responsive to the filling of the register to the storage capacity for selectively shifting the reading means from a first selected stage to a second selected stage, the second selected stage being the fixed number subsequent to the first selected stage to discard the fixed number of data bits stored between the first selected stage and the second selected stage and for operating the reading means to read out the bits from the second selected stage.
Claim 12
Dependent Claim
198 words
An elastic store for receiving frames of data, each frame consisting of a fixed number of data bits, comprising, a multistage data bit register having a storage capacity of at least one frame of data, each stage of the data bit register for storing a data bit; means for inserting the received data bits into the register at a rate controlled by the rate of the received data bits; means for reading the inserted data bits out of selected stages of the register at a rate controlled by a local clock, on a first in-first out basis; means jointly responsive to the inserting means and the reading means for determining a filling of the register with inserted bits awaiting readout; and means responsive to the filling of the register to the storage capacity for selectively shifting the reading means from a first selected stage to a second selected stage, the second selected stage being the fixed number subsequent to the first selected stage to discard the fixed number of data bits stored between the first selected stage and the second selected stage and for operating the reading means to read out the bits from the second selected stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-02 | 1978-12-02 | 1979-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-02 | 1982-12-02 | 1983-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-02 | 1986-12-02 | 1987-06-03 | $7700.00 | Window Closed / Lapsed |