Speed insensitive reading and writing apparatus for digital information

Claim 2

In a data handling system wherein bits of data are represented by signals in bit cells defined by displaced first and second transitions of a signal amplitude in a first direction and wherein the type of bit within a cell is defined by the position within a bit cell of a third transition of the signal amplitude in a second and opposite direction between said first and second transitions such that a first type of bit is represented when said third transition is closer to said first transition than said second transition and a second type of bit is represented when said third transition is closer to said second transition than said first transition, apparatus for identifying which type of bit is represented by the signal occurring within a bit cell comprising accumulating means for generating a first quantity related to the displacement between said first and third transition and storing said first quantity, deaccumulating means for generating a second quantity related to the displacement between said third and second transitions and subtracting said second quantity from said first quantity, and indicating means for indicating the type of bit as represented by the algebraic Sign of the remainder resulting from the subtraction.

Claim 3

In a data handling system wherein bits of data are represented by signals in bit cells defined by displaced first and second transitions of a signal amplitude in a first direction and wherein the type of bit within a cell is defined by the position within a bit cell of a third transition of the signal amplitude in a second and opposite direction between said first and second transitions such that a first type of bit is represented when said third transition is closer to said first transition than said second transition and a second type of bit is represented when said third transition is closer to said second transition than said first transition, apparatus for identifying which type of bit is represented by the signal occurring within a bit cell comprising accumulating means for generating a first quantity related to the displacement between said first and third transition and storing said first quantity, deaccumulating means for generating a second quantity related to the displacement between said third and second transitions and subtracting said second quantity from said first quantity, and indicating means for indicating the type of bit as represented by the algebraic Sign of the remainder resulting from the subtraction.

Claim 4

In a data handling system wherein bits of data are represented by signals in bit cells defined by displaced first and second transitions of a signal amplitude in a first direction and wherein the type of bit within a cell is defined by the position within a bit cell of a third transition of the signal amplitude in a second and opposite direction between said first and second transitions such that a first type of bit is represented when said third transition is closer to said first transition than said second transition and a second type of bit is represented when said third transition is closer to said second transition than said first transition, apparatus for identifying which type of bit is represented by the signal occurring within a bit cell comprising accumulating means for generating a first quantity related to the displacement between said first and third transition and storing said first quantity, deaccumulating means for generating a second quantity related to the displacement between said third and second transitions and subtracting said second quantity from said first quantity, and indicating means for indicating the type of bit as represented by the algebraic Sign of the remainder resulting from the subtraction.

Claim 5

The apparatus of claim 1 wherein said accumulating means comprises a first current generator of a first polarity of current and a capacitor connected to said first current generator to receive current therefrom during the time between said first and third transitions, and said deaccumulating means comprises a second current generator of a second and opposite polarity of current which is connectable to said capacitor during the time between said third and second transitions.

Claim 6

The apparatus of claim 2 wherein said indicating means includes means for periodically sampling the voltage across said capacitor.

Claim 7

The apparatus of claim 3 further comprising means operable at times related to one of said first and second transitions for activating said periodic sampling means and discharging said capacitor.

Claim 8

The apparatus of claim 1 wherein said accumulating means comprises a first pulse source for generating pulses at a given repetition rate, a multi-position up-down counter and means for connecting said up-down counter to said first pulse source and energizing said up-down counter to count in an up direction during the time between said first and third transitions, and said deaccumulating means comprises a second pulse source for generating pulses at said given repetition rate and means for connecting said up-down counter to said second pulse source for energizing said up-down counter to count in a down direction during the time between said third and second transitions.

Claim 9

The apparatus of claim 5 wherein said indicating means includes an algebraic sign indicator position in said updown counter and means for periodically sampling the sign indicator position of said up-down counter.

Claim 10

The apparatus of claim 6 further comprising means operable at times related to one of said first and second transitions for activating said periodic sampling means and clearing said up-down counter.

Claim 11

Data handling apparatus comprising: first means responsive to a digital input to generate a signal consisting of a plurality of periods in each of which the time ratio between the transitions between signal levels indicates the digital value represented in such period, said first means including means for generating clock pulses which delineate said periods, means for generating sequenced pulses occurring in each said periods, means responsive to said clock pulses for generating one of said signal levels and responsive to said sequenced pulses for generating the other of said levels, and means responsive to said digital input to block one of the sequenced pulses; second means for recording said signal as a series of rectangular pulses having leading and trailing edges; and third means for converting the thusly recorded signal into a further signal in which the presence and/or absence of pulses represents digital information including means for producing edge-defining pulses corresponding to said edges, quantity accumulating means, quantity generating means for increasing or decreasing the quantity accumulated in said quantity accumulating means in response to said edge-defining pulses, means for generating sample pulses in correspondence with said leading edges, and means for generating a digital signal dependent upon the magnitude of the accumulated quantity in said quantity accumulating means at the occurrence of said sample pulses.

Claim 12

Data handling apparatus comprising: first means responsive to a digital input to generate a signal consisting of a plurality of periods in each of which the time ratio between the transitions between signal levels indicates the digital value represented in such period, said first means including means for generating clock pulses which delineate said periods, means for generating sequenced pulses occurring in each said periods, means responsive to said clock pulses for generating one of said signal levels and responsive to said sequenced pulses for generating the other of said levels, and means responsive to said digital input to block one of the sequenced pulses; second means for recording said signal as a series of rectangular pulses having leading and trailing edges; and third means for converting the thusly recorded signal into a further signal in which the presence and/or absence of pulses represents digital information including means for producing edge-defining pulses corresponding to said edges, quantity accumulating means, quantity generating means for increasing or decreasing the quantity accumulated in said quantity accumulating means in response to said edge-defining pulses, means for generating sample pulses in correspondence with said leading edges, and means for generating a digital signal dependent upon the magnitude of the accumulated quantity in said quantity accumulating means at the occurrence of said sample pulses.

Claim 13

The apparatus of claim 8 wherein said quantity accumulating means is chargeable means for accumulating charge and said quantity generating means includes means for transferring charge to and for said chargeable means.

Claim 14

Apparatus as claimed in claim 9 comprising means to generate pulses delayed with respect to said leading edges and means responsive to the thusly delayed pulses to prevent the generation of said digital signal in correspondence to the first of the sample pulses.

Claim 15

Apparatus as claimed in claim 10 comprising means responsive to the last two said means to set the chargeable means in an initial reference state.

Claim 16

The apparatus of claim 8 wherein said quantity accumulating means includes a pulse counter controllable to count upward or downward and said quantity generating means includes a timing pulse source connectable to said pulse counter and means for controlling said counter to count upward or downward in accordance with the sensing of a leading or trailing edge.