US4024564A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having at least one PN junction and channel stopper surrounder by a protecture conducting layer
Assignee: Sony Corp
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Filing: 1975-08-13
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Granted: 1977-05-17
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Expires: 1995-08-13
Abstract
Abstract A semiconductor device is disclosed which has a first semiconductor layer of one conductivity type and low impurity concentration, a second semiconductor region of the opposite conductivity type forming a PN junction with the first semiconductor layer, a third semiconductor region of the first mentioned conductivity type formed in the first semiconductor layer which surrounds the PN junction and forms an LH junction with the first semiconductor layer, a passivating layer covering at least the PN and LH junctions, and a conductive layer extending on the passivating layer covering at least the inner periphery of the third region and connected to the first semiconductor layer through an electric barrier layer.
Inventors
- 👤 Takashi Shimada
- 👤 Shinishi Saiki
- 👤 Akio Kayanuma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:04
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/617; H10D99/00; H10P; H10P95/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
130 words
A semiconductor device comprising: a. a first semiconductor layer of one conductivity type having low impurity concentration; b. a second semiconductor region of the opposite conductivity type forming a PN junction with said first semiconductor layer; c. a third semiconductor region of said one conductivity type formed in said first semiconductor layer surrounding said PN junction, said third region having higher impurity concentration than that of said first layer; d. a passivation layer covering at least said PN junctions; and e. a conductive layer extending on said passivation layer covering at least the inner periphery of said third semiconductor region and connected to said first semiconductor layer through a fourth region of said opposite conductivity type, said fourth region forming an electric barrier layer with said first and third regions.
Claim 2
Dependent Claim
130 words
A semiconductor device comprising: a. a first semiconductor layer of one conductivity type having low impurity concentration; b. a second semiconductor region of the opposite conductivity type forming a PN junction with said first semiconductor layer; c. a third semiconductor region of said one conductivity type formed in said first semiconductor layer surrounding said PN junction, said third region having higher impurity concentration than that of said first layer; d. a passivation layer covering at least said PN junctions; and e. a conductive layer extending on said passivation layer covering at least the inner periphery of said third semiconductor region and connected to said first semiconductor layer through a fourth region of said opposite conductivity type, said fourth region forming an electric barrier layer with said first and third regions.
Claim 3
Dependent Claim
53 words
A semiconductor device as claimed in claim 1, in which said first semiconductor layer serves as a collector, said second semiconductor region serves as a base, and an emitter is diffused in said base at the same time of diffusing said third semiconductor region in said first semiconductor layer to form a transistor.
Claim 4
Dependent Claim
38 words
A semiconductor device as claimed in claim 1, in which said electric barrier layer is a PN junction formed between said first semiconductor layer of one conductivity type and said fourth semiconductor region of the opposite conductivity type.
Claim 5
Dependent Claim
31 words
A semiconductor device as claimed in claim 1, in which said electric barrier layer is positioned apart from a PN junction between said first semiconductor layer and said second semiconductor region.
Claim 6
Dependent Claim
21 words
A semiconductor device as claimed in claim 1, in which said electric barrier layer is formed in said third semiconductor region.
Claim 7
Dependent Claim
155 words
A semiconductor device comprising: a. a first semiconductor layer of one conductivity type having low impurity concentration; b. a second semiconductor region of the opposite conductivity type forming a first PN junction with said first semiconductor layer; c. a third semiconductor region of said one conductivity type having high impurity concentration formed in said first semiconductor region surrounding said first PN junction and forming a junction therewith; d. a fourth semiconductor region of said opposite conductivity type formed in said third semiconductor region and forming a second PN junction therewith; e. a passivation layer covering at least said first PN junction and said junction between said third region and said first region; and f. a conducting layer extending on said passivation layer covering at least the inner periphery of said third semiconductor region and connected to said first semiconductor layer through said fourth region, said fourth region forming a PN junction with said first region.
Claim 8
Dependent Claim
155 words
A semiconductor device comprising: a. a first semiconductor layer of one conductivity type having low impurity concentration; b. a second semiconductor region of the opposite conductivity type forming a first PN junction with said first semiconductor layer; c. a third semiconductor region of said one conductivity type having high impurity concentration formed in said first semiconductor region surrounding said first PN junction and forming a junction therewith; d. a fourth semiconductor region of said opposite conductivity type formed in said third semiconductor region and forming a second PN junction therewith; e. a passivation layer covering at least said first PN junction and said junction between said third region and said first region; and f. a conducting layer extending on said passivation layer covering at least the inner periphery of said third semiconductor region and connected to said first semiconductor layer through said fourth region, said fourth region forming a PN junction with said first region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-16 | 1980-11-15 | 1981-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-16 | 1984-11-15 | 1985-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-16 | 1988-11-15 | 1989-05-17 | $7700.00 | Window Closed / Lapsed |