← Back to Patent Explorer
US3684933A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device showing at least three successive zones of alternate opposite conductivity type

Assignee: TDK Micronas GmbH
•
Filing: 1971-06-21
•
Granted: 1972-08-15
•
Expires: 1991-06-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An annular region is inserted into the base region of a transistor, this region being of opposite conductivity type to said base region and surrounds the emitter region. When a reverse biasing potential is applied to the annular region and the emitter base junction is forward biased, the annular region serves as a channel stopper or interrupter to induced channels which would otherwise form at the surface of the base region and extend between the collector base and emitter base PN junctions.

Inventors

  • 👤 Egon Schulz
  • 👤 Ulrich Dolega
  • 👤 Johann Lang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 19:51
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D99/00; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 173 words
A semiconductor device having at least a first, second and third successive region of alternate opposite conductivity type forming a first pn-junction between said first and second regions and a second pn-junction between said second and third regions, an annular region inserted within said second region between said first and second pn-junctions, said annular region being of opposite conductivity type to said second region and forms a third pn-junction between said annular region and said second region, comprising: a fourth region formed within said third region, said fourth region being of opposite conductivity type to said third region, said fourth region forming a fourth pn-junction with said third region; and electrode means for electrically connecting said fourth region directly to said annular region so that when A reverse biasing potential is applied to said third region, said third and fourth pn-junctions are connected in series and said second, third and fourth pn-junctions are reversed biased, whereby the potential drop across said third pn-junction is less than the potential drop across said second pn-junction.
Claim 2
Dependent Claim 173 words
A semiconductor device having at least a first, second and third successive region of alternate opposite conductivity type forming a first pn-junction between said first and second regions and a second pn-junction between said second and third regions, an annular region inserted within said second region between said first and second pn-junctions, said annular region being of opposite conductivity type to said second region and forms a third pn-junction between said annular region and said second region, comprising: a fourth region formed within said third region, said fourth region being of opposite conductivity type to said third region, said fourth region forming a fourth pn-junction with said third region; and electrode means for electrically connecting said fourth region directly to said annular region so that when A reverse biasing potential is applied to said third region, said third and fourth pn-junctions are connected in series and said second, third and fourth pn-junctions are reversed biased, whereby the potential drop across said third pn-junction is less than the potential drop across said second pn-junction.
Claim 3
Dependent Claim 47 words
A semiconductor device according to claim 1 wherein said first region is formed within said second region, said second region being formed within said third region, said first and second pn-junctions extending toward one surface of said device, and said annular region completely surrounding said first region.
Claim 4
Dependent Claim 17 words
A semiconductor device according to claim 1 wherein said first region is the emitter of a transistor.

References Cited (Backward Citations)

US3177414A Cited
US3243669A Cited
US3416049A Cited
US3312882A Cited
US3427511A Cited
US3452206A Cited
US3479524A Cited
US3432920A Cited
US3500140A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-08-15 1976-02-14 1976-08-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-08-15 1980-02-14 1980-08-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-08-15 1984-02-14 1984-08-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag