First timing circuit controlled by a second timing circuit for generating long timing intervals

Claim 2

A timing circuit comprising, in combination: first and second charge store means: first and second comparators, each of the type having two reference voltage input levels, one relatively high and the other relatively low, and a signal voltage input terminal, and each for producing an output signal at a first level when the input signal present at said input terminal is higher than said high reference level, for producing an output signal at a second level when said input signal is lower than said low reference level, and for producing an output signal which remains at its previous value, either first or second, when said input signal is between said high and low levels, said first comparator connected at its signal input terminal to one terminal of said first charge storage means for sensing the voltage present there and said second comparator connected at its signal input terminal to one terminal of said second charge storage means for sensing the voltage present there; means responsive to the output signal of said first comparator for charging said first charge storage means when said output signal is at one level and discharging the same when said output signal is at its other level; and means for charging the second charge storage means, during the time said first charge storage means is discharging, when the output of said second comparator is at one level, and responsive to the output signal of said second comparator when at its other level, for discharging said second charge storage means.

Claim 3

A timing circuit as set forth in claim 1, wherein said means for charging said first charge storage means comprises two terminals across which an operating voltage may be applied and resistive means connected in series with said first charge storage means between said terminals, and wherein said means for discharging said first charge storage means comprising a normally open switch coupled across said first charge storage means and means responsive to said output signal of said first comparator when said signal is at its other level for closing said switch.

Claim 4

A timing circuit as set forth in claim 2 wherein said means for charging said first charge storage means has a substantially longer time constant than said means for discharging the same.

Claim 5

A timing circuit as set forth in claim 1 wherein said means for charging said second charge storage means comprises two terminals across which an operating voltage may be applied, a normally open switch and resistive means, said normally open switch and said resistive means being connected in series with said second charge storage means between said two terminals and means responsive to the output of said first comparator when said output is at said one level for closing said switch, and wherein said means for discharging said second charge storage means comprises a second normally open switch, this one coupled across said second charge storage means, and means for closing said second switch in response to the output of said second comparator, when said output is at its second level.

Claim 6

A timing circuit as set forth in claim 4, wherein said means for charging said first charge storage means comprises second resistive means, said second resistive means connected in series with said first charge storage means between said terminals, and wherein said means for discharging said first charge storage means comprising a third normally open switch coupled across said first charge storage means and means responsive to said output signal of said first comparator when said signal is at its other level for closing said third switch.

Claim 7

A timing circuit as set forth in claim 5 wherein each of said charge storage means comprises a capacitor.

Claim 8

A timing circuit as set forth in claim 5 wherein each means for charging a charge storage means has a substantially longer time constant than the means for discharging the same charge storage means.

Claim 9

A timing circuit comprising, in combination: first charge storage means; a comparator of the type having two reference voltage input levels, one relatively high and other relatively low, and a signal input terminal, for producing an output signal at a first level when the input signal present at said input terminal is higher than said high reference level, for producing an output signal at a second level when said input signal is lower than said low reference level, and for producing an output signal which remains at its previous value, either first or second, when said input signal is between said high and low levels, said comparator connected at its signal input terminal to one terminal of said charge storage means for sensing the voltage present there; a charging circuit connected across said first charge storage means for charging said first charge storage means when the output of said comparator is at one level; a discharging circuit having a substantially shorter time constant than said charging circuit, coupled across first charge storage means and responsive to the output of said comparator, when at its other level, for discharging said first charge storage means; a second charge storage means; means responsive to the output of said comparator for charging said second charge storage means only during each period said first charge storage means discharges; and means responsive to the voltage across said second charge storage means for discharging the same each time said second charge storage means charges to a predetermined level, said predetermined level being substantially larger than the charge accumulated by said second charge storage means during one period of discharge of said first charge storage means.

Claim 10

A timing circuit comprising, in combination: first charge storage means; a comparator of the type having two reference voltage input levels, one relatively high and other relatively low, and a signal input terminal, for producing an output signal at a first level when the input signal present at said input terminal is higher than said high reference level, for producing an output signal at a second level when said input signal is lower than said low reference level, and for producing an output signal which remains at its previous value, either first or second, when said input signal is between said high and low levels, said comparator connected at its signal input terminal to one terminal of said charge storage means for sensing the voltage present there; a charging circuit connected across said first charge storage means for charging said first charge storage means when the output of said comparator is at one level; a discharging circuit having a substantially shorter time constant than said charging circuit, coupled across first charge storage means and responsive to the output of said comparator, when at its other level, for discharging said first charge storage means; a second charge storage means; means responsive to the output of said comparator for charging said second charge storage means only during each period said first charge storage means discharges; and means responsive to the voltage across said second charge storage means for discharging the same each time said second charge storage means charges to a predetermined level, said predetermined level being substantially larger than the charge accumulated by said second charge storage means during one period of discharge of said first charge storage means.

Claim 11

In combination: means for producing a train of pulses of relatively short duration compared to the pulse period; capacitance means; means responsive to each pulse for charging said capacitance means during the pulse interval; a comparator connected across said capacitance means for sensing the voltage across the same, said comparator being of the type which produces an output voltage at a first level when the voltage across the capacitance means is lower than a given first value, which produces an output voltage at a second level when the voltage across the capacitance means is greater than a given second value higher than the first, and which produces an output voltage at its previous level when the voltage across said capacitance means is between said first and second levels; and means responsive to the output of said comparator for discharging said capacitance means when the output of said comparator is at its second level.

Claim 12

In combination: means for producing a train of pulses of relatively short duration compared to the pulse period; capacitance means; means responsive to each pulse for charging said capacitance means during the pulse interval; a comparator connected across said capacitance means for sensing the voltage across the same, said comparator being of the type which produces an output voltage at a first level when the voltage across the capacitance means is lower than a given first value, which produces an output voltage at a second level when the voltage across the capacitance means is greater than a given second value higher than the first, and which produces an output voltage at its previous level when the voltage across said capacitance means is between said first and second levels; and means responsive to the output of said comparator for discharging said capacitance means when the output of said comparator is at its second level.