Timer apparatus utilizing operational amplifier integrating means

Claim 2

A circuit for developing an output signal a predetermined time after the application of an applied input signal comprising: integration means, responsive to said applied signal, having a predetermined linear range of integration in which said integrator develops a signal representative of the mathematical integral of said applied signal, said integration means developing a signal at a terminal thereof which is at virtual ground only when said integration means is within said linear range of integration; and comparator means responsive to the difference between said signal at said terminal and an applied reference signal for developing said output signal.

Claim 3

The circuit of claim 1 wherein the magnitude of said applied reference signal is proportional to the magnitude of the output signal of said comparator means.

Claim 4

A timer circuit comprising: integrator means exhibiting a first range for linearly integrating a positive signal applied to said timer circuit and exhibiting a second range for linearly integrating a negative signal applied to said timer circuit, said integrator means further exhibiting a first saturated state when the integral of said positive applied signal is outside said first linear integration range and a second saturated state when the integral of said negative applied signal is outside said second linear integration range, said integrator means developing an indication signal which is at virtual ground whenever said integrator is operating within said first or second lineAr integrating range, said indication signal being a first predetermined potential whenever said integrator means is operating within said first saturated state and a second predetermined potential whenever said integrator means is operating within said second saturated state; and output means for comparing said indication signal with an applied reference signal, said output means developing an output signal of a first predetermined level when said indication signal is more positive than said reference signal and developing an output signal of a second predetermined level when said indication signal is more negative than said reference signal.

Claim 5

A timer circuit comprising: integrator means exhibiting a first range for linearly integrating a positive signal applied to said timer circuit and exhibiting a second range for linearly integrating a negative signal applied to said timer circuit, said integrator means further exhibiting a first saturated state when the integral of said positive applied signal is outside said first linear integration range and a second saturated state when the integral of said negative applied signal is outside said second linear integration range, said integrator means developing an indication signal which is at virtual ground whenever said integrator is operating within said first or second lineAr integrating range, said indication signal being a first predetermined potential whenever said integrator means is operating within said first saturated state and a second predetermined potential whenever said integrator means is operating within said second saturated state; and output means for comparing said indication signal with an applied reference signal, said output means developing an output signal of a first predetermined level when said indication signal is more positive than said reference signal and developing an output signal of a second predetermined level when said indication signal is more negative than said reference signal.

Claim 6

The timer circuit of claim 3 wherein said applied reference signal is a first predetermined negative voltage when said timer output signal is at said first predetermined output level and said reference voltage is a first predetermined positive voltage when said timer output signal is at said second predetermined output level.

Claim 7

The timer circuit of claim 4 further comprising means for controlling the integration rate of said integrator means in response to the polarity of said timer input signal, said control means establishing a first integration rate when said timer input signal is positive and a second integration rate when said timer input signal is negative.

Claim 8

A circuit for delaying an applied signal comprising: an integrating circuit including an operational amplifier having noninverting and inverting input terminals and an output terminal, a capacitor connected between said amplifier output terminal and said amplifier inverting input terminal and a resistor connected between said inverting amplifier input terminal and the input terminal of said delay circuit; means for establishing a predetermined voltage level at said amplifier inverting input terminal when said inverting input is not at virtual ground; and means responsive to said predetermined voltage level and an applied reference signal for developing an output voltage of a first potential when said predetermined voltage level is greater than said reference voltage and for developing an output voltage of a second potential when said predetermined voltage is less than said reference voltage.

Claim 9

A circuit for delaying an applied signal comprising: an integrating circuit including an operational amplifier having noninverting and inverting input terminals and an output terminal, a capacitor connected between said amplifier output terminal and said amplifier inverting input terminal and a resistor connected between said inverting amplifier input terminal and the input terminal of said delay circuit; means for establishing a predetermined voltage level at said amplifier inverting input terminal when said inverting input is not at virtual ground; and means responsive to said predetermined voltage level and an applied reference signal for developing an output voltage of a first potential when said predetermined voltage level is greater than said reference voltage and for developing an output voltage of a second potential when said predetermined voltage is less than said reference voltage.

Claim 10

The circuit of claim 6 wherein the polarity of said predetermined voltage at said inverting input is determined by the polarity of the input signal to said timer circuit.

Claim 11

The circuit of claim 7 wherein said reference signal is a predetermined fractional part of said output voltage.

Claim 12

A timer circuit comprising: an integrator circuit including an operational amplifier having an inverting input terminal, a noninverting input terminal, an output terminal, and a capacitor connected between said operational amplifier inverting input terminal and said operational amplifier output terminal; means for connecting said amplifier inverting input terminal to the input terminal of said timer circuit; and a comparator circuit for detecting the potential at said operational amplifier inverting input terminal, said comparator circuit having first and second comparator input terminals and an output terminal, said first comparator input terminal connected to said amplifier inverting input terminal and said second comparator input terminal supplied with a first reference voltage which is proportional to the output signal of said comparator.

Claim 13

A timer circuit comprising: an integrator circuit including an operational amplifier having an inverting input terminal, a noninverting input terminal, an output terminal, and a capacitor connected between said operational amplifier inverting input terminal and said operational amplifier output terminal; means for connecting said amplifier inverting input terminal to the input terminal of said timer circuit; and a comparator circuit for detecting the potential at said operational amplifier inverting input terminal, said comparator circuit having first and second comparator input terminals and an output terminal, said first comparator input terminal connected to said amplifier inverting input terminal and said second comparator input terminal supplied with a first reference voltage which is proportional to the output signal of said comparator.

Claim 14

The timer circuit of claim 9 wherein said means for connecting said amplifier inverting input terminal to said timer circuit input terminal includes control means, responsive to the polarity of the signal applied to said timer circuit input terminal, for controlling the integration rate of said integrator circuit.

Claim 15

The timer circuit of claim 9 further comprising a second comparator circuit having first and second input terminals and an output terminal, said second comparator first input terminal connected to said integrator amplifier output terminal, said second comparator second input terminal supplIed with a second reference voltage which is representative of the output of said second comparator, said second comparator output terminal connected to said output terminal of said timer circuit, said means for connecting said amplifier inverting input terminal to said timer circuit input terminal including a logic circuit responsive to the signal applied to said timer circuit, responsive to the output of said comparator circuit, and responsive to the said output signal of said second comparator.

Claim 16

A time-delay circuit comprising: first and second operational amplifiers, each having an inverting and noninverting input terminal and an output terminal, said inverting input terminals of said first and second amplifiers commonly connected, said noninverting input terminal of said first amplifier connected to a terminal of fixed potential; a capacitor, connected between said first amplifier output terminal and said commonly connected inverting input terminals; a first resistor connected between the input terminal of said time-delay circuit and said commonly connected inverting input terminals; a second resistor connected between said commonly connected inverting input terminals and said terminal of fixed potential; a third resistor connected between said second amplifier noninverting input terminal and said terminal of fixed potential; and a fourth resistor connected between said second amplifier output terminal and said second amplifier noninverting input terminal.

Claim 17

A time-delay circuit comprising: first and second operational amplifiers, each having an inverting and noninverting input terminal and an output terminal, said inverting input terminals of said first and second amplifiers commonly connected, said noninverting input terminal of said first amplifier connected to a terminal of fixed potential; a capacitor, connected between said first amplifier output terminal and said commonly connected inverting input terminals; a first resistor connected between the input terminal of said time-delay circuit and said commonly connected inverting input terminals; a second resistor connected between said commonly connected inverting input terminals and said terminal of fixed potential; a third resistor connected between said second amplifier noninverting input terminal and said terminal of fixed potential; and a fourth resistor connected between said second amplifier output terminal and said second amplifier noninverting input terminal.

Claim 18

A time-delay circuit including means for restoring a predetermined minimum duty-cycle to an applied input signal comprising: first and second operational amplifiers, each of said amplifiers including an inverting input terminal, a noninverting input terminal and an output terminal, said inverting input terminals commonly connected, and said noninverting input terminal of said first amplifier connected to a terminal of fixed potential; a capacitor connected between said first amplifier output terminal and said commonly connected inverting input terminals; a first resistor connected between said commonly connected amplifier inverting input terminals and said terminal of fixed potential; a second resistor connected between said second amplifier noninverting input terminal and said terminal of fixed potential; a third resistor connected between said second amplifier noninverting input terminal and said second amplifier output terminal; a comparator circuit responsive to the signal level at said first amplifier output terminal and an applied reference signal, said comparator circuit output connected to the output terminal of said time delay circuit; a logic circuit responsive to multiple input signals including the output of said second amplifier, the output of said comparator circuit, and the input signal to said time-delay circuit; and a fourth resistor for connecting the output of said logic circuit to said commonly connected inverting inputs of said first and second amplifiers.

Claim 19

A time-delay circuit including means for restoring a predetermined minimum duty-cycle to an applied input signal comprising: first and second operational amplifiers, each of said amplifiers including an inverting input terminal, a noninverting input terminal and an output terminal, said inverting input terminals commonly connected, and said noninverting input terminal of said first amplifier connected to a terminal of fixed potential; a capacitor connected between said first amplifier output terminal and said commonly connected inverting input terminals; a first resistor connected between said commonly connected amplifier inverting input terminals and said terminal of fixed potential; a second resistor connected between said second amplifier noninverting input terminal and said terminal of fixed potential; a third resistor connected between said second amplifier noninverting input terminal and said second amplifier output terminal; a comparator circuit responsive to the signal level at said first amplifier output terminal and an applied reference signal, said comparator circuit output connected to the output terminal of said time delay circuit; a logic circuit responsive to multiple input signals including the output of said second amplifier, the output of said comparator circuit, and the input signal to said time-delay circuit; and a fourth resistor for connecting the output of said logic circuit to said commonly connected inverting inputs of said first and second amplifiers.

Claim 20

The time-delay circuit of claim 13 wherein said logic circuit performs the operation described by the Boolean expression VAVB + VAVC + VAVBVC where VA, VB, and VC are respectively representative of the voltage levels at said output terminal of said second amplifier, said input of said time-delay circuit, and said output of said comparator circuit.

Claim 21

The time-delay circuit of claim 14 wherein said comparator circuit includes a third operational amplifier having an inverting input, a noninverting input, and an output terminal, said inverting input of said third amplifier connected to the output terminal of said first amplifier, said third amplifier output terminal connected to said time-delay circuit output terminal, and said third amplifier noninverting input terminal connected to a reference signal which is developed from the output signal of said time-delay circuit.

Claim 22

The time-delay circuit of claim 15 wherein said comparator circuit reference signal is established by fifth and sixth resistors serially connected between two terminals of fixed potential and a seventh resistor connected between said comparator output terminal and the junction of said fifth and sixth resistors, the common junction of said fifth, sixth, and seventh resistors connected to the noninverting input terminal of said third operational amplifier.