US3693101A
Expired / Lapsed
US
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Time delay circuit
Assignee: Motors Liquidation Co
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Filing: 1971-09-07
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Granted: 1972-09-19
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Expires: 1991-09-07
Abstract
Abstract A train of variable width pulses is time delayed by a circuit comprising an array of operational amplifiers arranged as comparators. One comparator includes a time delay and filter circuit for discriminating against very short pulses and reproducing all other pulses after a time delay. Two other comparators have time delays of equal length responsive to the leading and trailing ends of each pulse and control a final comparator which reproduces the original pulse train except for the very short pulses.
Inventors
- 👤 Philip K Trimble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:31
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273; H; H03; H03K; H03K5/00; H03K5/13
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
204 words
A time delay circuit for delaying a train of variable width square wave pulses comprising first switching means for changing state upon receipt of an input pulse to produce a first output signal including a first time delay means for delaying a change of state of the first switching means only upon removal of the input pulse, second switching means responsive to the first output signal to produce a second output signal including a second time delay means for delaying the change of state of the second switching means only upon receipt of the first output signal, the periods of the first and second time delays being substantially equal, third switching means responsive to the second output signal for changing state upon receipt of the second output signal to initiate an output pulse, and further responsive to the first output signal to terminate the output pulse when both the first and second output signal are terminated, means for resetting the second switching means in response to an output pulse in the absence of the input pulse, and means responsive to the output pulse for inhibiting the effects of the input pulse on the first timing means in the absence of the second output signal.
Claim 2
Dependent Claim
204 words
A time delay circuit for delaying a train of variable width square wave pulses comprising first switching means for changing state upon receipt of an input pulse to produce a first output signal including a first time delay means for delaying a change of state of the first switching means only upon removal of the input pulse, second switching means responsive to the first output signal to produce a second output signal including a second time delay means for delaying the change of state of the second switching means only upon receipt of the first output signal, the periods of the first and second time delays being substantially equal, third switching means responsive to the second output signal for changing state upon receipt of the second output signal to initiate an output pulse, and further responsive to the first output signal to terminate the output pulse when both the first and second output signal are terminated, means for resetting the second switching means in response to an output pulse in the absence of the input pulse, and means responsive to the output pulse for inhibiting the effects of the input pulse on the first timing means in the absence of the second output signal.
Claim 3
Dependent Claim
261 words
A time delay circuit for delaying a train of variable width square wave pulses comprising a signal conditioning circuit responsive to each square wave pulse for generating an input pulse equal in width to the square wave pulse and including a filter and time delay circuit for delaying the input pulse for a predetermined time after the square wave pulse and inhibiting any input pulse of duration less than the predetermined time, first switching means for changing state upon receipt of an input pulse to produce a first output signal including a first time delay means for delaying a change of state of the first switching means only upon removal of the input pulse, second switching means responsive to the first output signal to produce a second output signal including a second time delay means for delaying the change of state of the second switching means only upon receipt of the first output signal, the periods of the first and second time delays being substantially equal, third switching means responsive to the second output signal for changing state upon receipt of the second output signal to initiate an output pulse, and further responsive to the first output signal to terminate the output pulse when both the first and second output signals are termInated, means for resetting the second switching means in response to the output pulse in the absence of the input pulse and means responsive to the output pulse for inhibiting the effects of the input pulse on the first timing means in the absence of the second output signal.
Claim 4
Dependent Claim
261 words
A time delay circuit for delaying a train of variable width square wave pulses comprising a signal conditioning circuit responsive to each square wave pulse for generating an input pulse equal in width to the square wave pulse and including a filter and time delay circuit for delaying the input pulse for a predetermined time after the square wave pulse and inhibiting any input pulse of duration less than the predetermined time, first switching means for changing state upon receipt of an input pulse to produce a first output signal including a first time delay means for delaying a change of state of the first switching means only upon removal of the input pulse, second switching means responsive to the first output signal to produce a second output signal including a second time delay means for delaying the change of state of the second switching means only upon receipt of the first output signal, the periods of the first and second time delays being substantially equal, third switching means responsive to the second output signal for changing state upon receipt of the second output signal to initiate an output pulse, and further responsive to the first output signal to terminate the output pulse when both the first and second output signals are termInated, means for resetting the second switching means in response to the output pulse in the absence of the input pulse and means responsive to the output pulse for inhibiting the effects of the input pulse on the first timing means in the absence of the second output signal.
Claim 5
Dependent Claim
231 words
A time delay circuit for delaying a train of variable width square wave pulses comprising a first operational amplifier connected as a comparator circuit for changing state upon receipt of an input pulse to produce a first output signal including a first time delay circuit at the input thereof for delaying a change of state of the comparator circuit only upon removal of the input pulse, a second operational amplifier connected as a comparator circuit responsive to the first output signal to produce a second output signal including a second time delay circuit at the input thereof for delaying the change of state of the second comparator circuit only upon receipt of the first output signal, the time delays of the first and second time delay circuits being substantially equal, a third operational amplifier connected as a comparator circuit responsive to the second output signal for changing state upon receipt of the second output signal to initiate an output pulse, and further responsive to the first output signal to terminate the output pulse when both the first and second output signal are terminated, means for resetting the second switching means in response to the output pulse in the absence of the input pulse, and means responsive to the output pulse for inhibiting the effects of the input pulse on the first timing means in the absence of the second output signal.
Claim 6
Dependent Claim
231 words
A time delay circuit for delaying a train of variable width square wave pulses comprising a first operational amplifier connected as a comparator circuit for changing state upon receipt of an input pulse to produce a first output signal including a first time delay circuit at the input thereof for delaying a change of state of the comparator circuit only upon removal of the input pulse, a second operational amplifier connected as a comparator circuit responsive to the first output signal to produce a second output signal including a second time delay circuit at the input thereof for delaying the change of state of the second comparator circuit only upon receipt of the first output signal, the time delays of the first and second time delay circuits being substantially equal, a third operational amplifier connected as a comparator circuit responsive to the second output signal for changing state upon receipt of the second output signal to initiate an output pulse, and further responsive to the first output signal to terminate the output pulse when both the first and second output signal are terminated, means for resetting the second switching means in response to the output pulse in the absence of the input pulse, and means responsive to the output pulse for inhibiting the effects of the input pulse on the first timing means in the absence of the second output signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-19 | 1976-03-20 | 1976-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-19 | 1980-03-20 | 1980-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-19 | 1984-03-20 | 1984-09-19 | $7700.00 | Window Closed / Lapsed |