US3887823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential amplifier pulse delay circuit
Assignee: Sony Corp
•
Filing: 1973-12-18
•
Granted: 1975-06-03
•
Expires: 1993-12-18
Abstract
Abstract A pulse delay circuit including a differential amplifier with two transistors, a clamping transistor, and a resistor capacitor time constant circuit connected to the base input terminal of one of the differential amplifier transistors. A reference voltage is connected to the base input terminal of the other differential transistor. Pulses to have at least one edge delayed are applied to the clamping transistor to clamp the capacitor to a predetermined charge level and the first differential transistor to cut-off. At the end of the pulse, voltage across the capacitor starts to change, and after a predetermined delay time, the voltage at the input terminal of the first differential transistor reaches the reference voltage level, causing the first differential transistor to become conductive and causing the second to become non-conductive by differential operation.
Inventors
- 👤 Akira Nikami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:39
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K17/00; H03K17/28
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
192 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising: 1. first and second differentially connected transistors having their emitters connected together, 2. first and second input terminals connected, respectively, to the bases of said first and second transistors, 3. an output terminal, 4. means connecting said output terminal to the collector of one of said differentially connected transistors, and 5. means connecting said connected together emitters and the collectors of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first and second clamping circuits for activating the latter; and G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not activated.
Claim 2
Dependent Claim
192 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising: 1. first and second differentially connected transistors having their emitters connected together, 2. first and second input terminals connected, respectively, to the bases of said first and second transistors, 3. an output terminal, 4. means connecting said output terminal to the collector of one of said differentially connected transistors, and 5. means connecting said connected together emitters and the collectors of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first and second clamping circuits for activating the latter; and G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not activated.
Claim 3
Dependent Claim
16 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
Claim 4
Dependent Claim
16 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
Claim 5
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 6
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 7
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 8
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 9
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 10
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 11
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 12
Dependent Claim
11 words
first and second differentially connected transistors having their emitters connected together,
Claim 13
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 14
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 15
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 16
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 17
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 18
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 19
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 20
Dependent Claim
16 words
first and second input terminals connected, respectively, to the bases of said first and second transistors,
Claim 21
Dependent Claim
43 words
The delay circuit of claim 1 wherein said time constant circuit comprises: A. a capacitor and a resistor connected in series between said power supply terminals; and B. a common circuit point between said capacitor and resistor connected to said first input terminal.
Claim 22
Dependent Claim
45 words
The delay circuit of claim 1 wherein said time constant circuit comprises a capacitor and a resistor connected in parallel between one of said power supply terminals and said first input terminal, said clamping circuit being connected to the other of said power supply terminals.
Claim 23
Dependent Claim
3 words
an output terminal,
Claim 24
Dependent Claim
3 words
an output terminal,
Claim 25
Dependent Claim
3 words
an output terminal,
Claim 26
Dependent Claim
3 words
an output terminal,
Claim 27
Dependent Claim
3 words
an output terminal,
Claim 28
Dependent Claim
3 words
an output terminal,
Claim 29
Dependent Claim
3 words
an output terminal,
Claim 30
Dependent Claim
3 words
an output terminal,
Claim 31
Dependent Claim
16 words
means connecting said output terminal to the collector of one of said differentially connected transistors, and
Claim 32
Dependent Claim
16 words
means connecting said output terminal to the collector of one of said differentially connected transistors, and
Claim 33
Dependent Claim
16 words
means connecting said output terminal with the collector of one of said differentially connected transistors, and
Claim 34
Dependent Claim
16 words
means connecting said output terminal with the collector of one of said differentially connected transistors, and
Claim 35
Dependent Claim
15 words
means connecting said output terminal with the collector of one of said differentially connected transistors,
Claim 36
Dependent Claim
15 words
means connecting said output terminal with the collector of one of said differentially connected transistors,
Claim 37
Dependent Claim
16 words
means connecting said output terminal to the collector of one of said differentially connected transistors, and
Claim 38
Dependent Claim
16 words
means connecting said output terminal to the collector of one of said differentially connected transistors, and
Claim 39
Dependent Claim
20 words
The delay circuit of claim 1, further comprising a unidirectionally conductive semiconductor device connected in series between said input terminals.
Claim 40
Dependent Claim
63 words
The delay circuit of claim 1, further comprising A. a constant current source connected in series between said emitters and said first power supply terminal and including an additional transistor; and B. means connecting said second clamping circuit to said additional transistor to make said transistor in said constant current source nonconductive for the duration of each of said pulses to be delayed.
Claim 41
Dependent Claim
125 words
means connecting said connected together emitters and the collectors of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first and second clamping circuits for activating the latter; and G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not activated.
Claim 42
Dependent Claim
125 words
means connecting said connected together emitters and the collectors of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first and second clamping circuits for activating the latter; and G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not activated.
Claim 43
Dependent Claim
22 words
a high resistance resistor connected in series between said emitters of said differentially connected transistors and said first power supply terminal, and
Claim 44
Dependent Claim
22 words
a high resistance resistor connected in series between said emitters of said differentially connected transistors and said first power supply terminal, and
Claim 45
Dependent Claim
149 words
means connecting the emitters and collectors of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first clamping circuit; G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is nonconductive; and H. amplifying means connecting the collector of said second differentially connected transistor to said second clamping circuit to keep said second clamping circuit nonconductive as long as said second differentially connected transistor is conductive.
Claim 46
Dependent Claim
149 words
means connecting the emitters and collectors of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first clamping circuit; G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is nonconductive; and H. amplifying means connecting the collector of said second differentially connected transistor to said second clamping circuit to keep said second clamping circuit nonconductive as long as said second differentially connected transistor is conductive.
Claim 47
Dependent Claim
173 words
means connecting the collectors and emitters of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said second input terminal of the differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first and second clamping circuits; G. a reference voltage circuit connected to said second input teminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not conductive; and H. a positive feedback connection from the collector of said first differentially connected transistor to the base of said second differentially connected transistor, with both of said clamping circuits being conductive for the duration of each of said pulses to clamp both of said input terminals to a nonconductive level.
Claim 48
Dependent Claim
173 words
means connecting the collectors and emitters of said differentially connected transistors to said first and second power supply terminals, respectively; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. a second clamping circuit connected to said second input terminal of the differential amplifier to control the conductivity of said second transistor; F. pulse input means to apply pulses to be delayed to said first and second clamping circuits; G. a reference voltage circuit connected to said second input teminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not conductive; and H. a positive feedback connection from the collector of said first differentially connected transistor to the base of said second differentially connected transistor, with both of said clamping circuits being conductive for the duration of each of said pulses to clamp both of said input terminals to a nonconductive level.
Claim 49
Dependent Claim
153 words
means connecting the collectors of said differentially connected transistors to said second power supply terminal; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. pulse input means to apply pulses to be delayed to said first clamping circuit; F. unidirectionally conductive means constituting a second clamping circuit connected to said pulse input means to be made conductive for the duration of each of said pulses and connected to the emitters of said differentially connected transistors to bias said emitters to cause both of said differentially connected transistors to be nonconductive for the duration of each of said pulses; and G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not conductive.
Claim 50
Dependent Claim
153 words
means connecting the collectors of said differentially connected transistors to said second power supply terminal; C. a time constant circuit connected to said first input terminal; D. a first clamping circuit connected to said first input terminal to control the conductivity of said first transistor; E. pulse input means to apply pulses to be delayed to said first clamping circuit; F. unidirectionally conductive means constituting a second clamping circuit connected to said pulse input means to be made conductive for the duration of each of said pulses and connected to the emitters of said differentially connected transistors to bias said emitters to cause both of said differentially connected transistors to be nonconductive for the duration of each of said pulses; and G. a reference voltage circuit connected to said second input terminal, whereby said second transistor is normally conductive when said first transistor is nonconductive and said second clamping circuit is not conductive.
Claim 51
Dependent Claim
16 words
A delay circiut comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
Claim 52
Dependent Claim
16 words
A delay circiut comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
Claim 53
Dependent Claim
41 words
The delay circuit of claim 6 in which said unidirectionally conductive means comprises a further transistor comprising an emitter-collector circuit connected in series between said emitters and said second power supply terminal, and a base connected to said pulse input means.
Claim 54
Dependent Claim
26 words
The delay circuit of claim 6 in which said unidirectionally conductive means comprises a diode connected in series between said pulse input means and said emitters.
Claim 55
Dependent Claim
16 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
Claim 56
Dependent Claim
16 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
Claim 57
Dependent Claim
16 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
Claim 58
Dependent Claim
16 words
A delay circuit comprising: A. first and second power supply terminals; B. a differential amplifier comprising:
References Cited (Backward Citations)
US3514641A
Cited
US3365586A
Cited
US3471717A
Cited
US3364441A
Cited
US3504202A
Cited
US3818356A
Cited
US3654494A
Cited
US3571626A
Cited
US3742257A
Cited
US3725673A
Cited
US3735150A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-02 | 1978-12-02 | 1979-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-02 | 1982-12-02 | 1983-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-02 | 1986-12-02 | 1987-06-03 | $7700.00 | Window Closed / Lapsed |