Adaptive delta modulation system for correcting mistracking

Claim 2

In an adaptive modulation apparatus including a means for comparing an analog input signal with an analog feedback signal to produce an adaptive delta modulation output signal wherein each bit of said output signal has a quantized stepsize, an adaptation logic circuit means connected to receive said output signal from said comparison means for monitoring and determining the stepsize value for each subsequent bit produced by said comparing means and generating a stepsize value signal, and an integrator circuit connected to receive said stepsize value signal from said adaptive logic circuit and producing said analog feedback signal, wherein the improvement in said adaptive logic circuit comprises: first means for counting several preceding bits of said adaptive delta modulation output signal and producing a first stepsize change command signal when a predetermined number of identical bits are counted and a second stepsize change command signal when a predetermined number of sequentially alternating bits are counted; second means for counting the number of bits of said adaptive delta modulation output signal from the time of the last stepsize change and producing a third stepsize change command signal when said number of bits counted reaches a number which is predetermined according to said quantized stepsize at that time; and third means for receiving said first, second and third stepsize change command signals, generating said stepsize value signal in response to any one of said command signals and changing said stepsize value signal in accordance therewith.

Claim 3

An adaptive delta modulation apparatus which includes a comparator provided with a first input terminal for receiving an analog input signal and a second input terminal, an adaptation logic circuit for receiving the output of said comparator, and an integrator circuit for receiving the output of said adaptation logic circuit and supplying an output to said second input terminal of said comparator, wherein said adaptation logic circuit comprises: a. a first counter connected to the output of said comparator for counting the number of successive identical signal bits within a sequence of adaptive delta modulation bits; b. a second counter connected to the output of said comparator for counting the number of successive alternating signal bits within a sequence of the adaptive delta modulation bits; c. an up and down counter for counting up in accordance with the output of said first counter and counting down in accordance with the output of said second counter; d. a first logic circuit for receiving the output of said up and down counter, inhibiting a count up of said up and down counter when said first logic circuit detects a value corresponding to the maximum step value of said up and down counter, and inhibiting a count down of said up and down counter when said first logic circuit detects a value corresponding to the minimum step value of said up and down counter; e. a second logic circuit for reading the value of said up and down counter, detecting the stepsize used each time and determining a threshold value in accordance with said stepsize; f. a third counter for receiving the output of said second logic circuit, counting clock pulses starting from the time when said stepsize is changed and causing said up and down counter to count down by one stepsize when the counted value of clock pulses reaches said threshold value determined by said second logic circuit; and g. an integrating step generator for reading the value of said up and down counter, converting said value into an analog signal, switching the polarity of said analog signal in response to the output value of said comparator and applying said analog signal to said integrator circuit.

Claim 4

An adaptive delta modulation apparatus which includes a comparator provided with a first input terminal for receiving an analog input signal and a second input terminal, an adaptation logic circuit for receiving the output of said comparator, and an integrator circuit for receiving the output of said adaptation logic circuit and supplying an output to said second input terminal of said comparator, wherein said adaptation logic circuit comprises: a. a first counter connected to the output of said comparator for counting the number of successive identical signal bits within a sequence of adaptive delta modulation bits; b. a second counter connected to the output of said comparator for counting the number of successive alternating signal bits within a sequence of the adaptive delta modulation bits; c. an up and down counter for counting up in accordance with the output of said first counter and counting down in accordance with the output of said second counter; d. a first logic circuit for receiving the output of said up and down counter, inhibiting a count up of said up and down counter when said first logic circuit detects a value corresponding to the maximum step value of said up and down counter, and inhibiting a count down of said up and down counter when said first logic circuit detects a value corresponding to the minimum step value of said up and down counter; e. a second logic circuit for reading the value of said up and down counter, detecting the stepsize used each time and determining a threshold value in accordance with said stepsize; f. a third counter for receiving the output of said second logic circuit, counting clock pulses starting from the time when said stepsize is changed and causing said up and down counter to count down by one stepsize when the counted value of clock pulses reaches said threshold value determined by said second logic circuit; and g. an integrating step generator for reading the value of said up and down counter, converting said value into an analog signal, switching the polarity of said analog signal in response to the output value of said comparator and applying said analog signal to said integrator circuit.

Claim 5

An adaptive delta modulation apparatus according to claim 2, further comprising, a. a time delay circuit connected to the output of said comparator so as to delay the bits of said adaptive modulation with the time delay corresponding to one sample period, and b. an exclusive OR gate connected to the output of said time delay circuit, for sending 1 to said adaptation logic circuit when two successive bits are of the same kind, and 0 when two successive bits are of a different kind.

Claim 6

An adaptive delta modulation apparatus according to claim 2, wherein said adaptation logic circuit further comprises, a. a first threshold circuit connected between said first counter and said up and down counter for detecting the time at which the output of said first counter reaches the predetermined value, and b. a second threshold circuit which is connected between said second counter and said up and down counter and detects the time at which the output of said second counter reaches the predetermined value.

Claim 7

An adaptive delta modulation apparatus according to claim 4, wherein said adaptation logic circuit further comprises an inverter provided between the output of said first threshold circuit and said up and down counter, whereby said up and down counter counts up when the output of said threshold circuit and the output of said second logic circuits become 1 at the same time.