Differential pulse code modulation system employing periodic modulator step modification

Claim 2

In a differential pulse code modulation coder utilizing a delta modulator and including a delta modulation output pulse counter for accumulating counts of pulses produced in sampling intervals of said modulator, means operating said counter over an initial M-a intervals of a group of M delta modulation sampling intervals, a and M being positive real integers at least equal to one and greater than one, respectively, and M being greater than a, said counter including means for providing a bit-parallel binary coded output signal representing the state of the counter, means for detecting the presence or absence of a delta modulator output pulse in a final intervals of said group, and means responsive to the output of said detecting means for adding a bits to the output of said counter as new least significant bIt positions for representing the state of said detecting means output signal.

Claim 3

In combination, a delta modulator for producing, in successive modulator sampling intervals, signals indicating the present nature of an input analog signal with respect to such analog signal in a prior sampling interval, said modulator including means responsive to said indicating signals for modifying modulator operation in steps of predetermined unit size, means for detecting the presence or absence of an indicating signal in at least one, but much less than all, periodically recurring one of said sampling intervals, the recurrence period of said one interval being much greater than the recurrence period of said successive modulator sampling intervals, and means, responsive to an output of said detecting means, for effecting a change in the operation of said modifying means by a fixed portion of a unit step and completing such change prior to the next succeeding recurrence of said one sampling interval.

Claim 4

In combination, a delta modulator for producing, in successive modulator sampling intervals, signals indicating the present nature of an input analog signal with respect to such analog signal in a prior sampling interval, said modulator including means responsive to said indicating signals for modifying modulator operation in steps of predetermined unit size, means for detecting the presence or absence of an indicating signal in at least one, but much less than all, periodically recurring one of said sampling intervals, the recurrence period of said one interval being much greater than the recurrence period of said successive modulator sampling intervals, and means, responsive to an output of said detecting means, for effecting a change in the operation of said modifying means by a fixed portion of a unit step and completing such change prior to the next succeeding recurrence of said one sampling interval.

Claim 5

The combination in accordance with claim 2 in which said delta modulator includes integrating means comprising resistance means, capacitance means, and means connecting said resistance means and capacitance means in parallel, and said modifying means includes means applying said indicating signals to said integrating means.

Claim 6

The combination in accordance with claim 3 in which said resistance means comprises first and second resistors connected in series in the parallel connection with said capacitance means, and said effecting means comprises means coupling the output of said detecting means across said second resistor.

Claim 7

In a system wherein a pulse train representing a delta modulated format of an analog signal includes recurring pulse train periods each containing plural successive pulse times in which a pulse may or may not be present, and wherein the pulse train is utilized to control circuit means for reproducing such analog signal, means for indicating whether or not a pulse is present in said train in a pulse time near the end of each of said periods, and means responsive to the output of said indicating means for periodically applying to said circuit means a signal for partially modifying the signal reproducing effect of the last-mentioned pulse time of said pulse train by a predetermined fraction of such effect.

Claim 8

In a system wherein a pulse train representing a delta modulated format of an analog signal includes recurring pulse train periods each containing plural successive pulse times in which a pulse may or may not be present, and wherein the pulse train is utilized to control circuit means for reproducing such analog signal, means for indicating whether or not a pulse is present in said train in a pulse time near the end of each of said periods, and means responsive to the output of said indicating means for periodically applying to said circuit means a signal for partially modifying the signal reproducing effect of the last-mentioned pulse time of said pulse train by a predetermined fraction of such effect.

Claim 9

The system in accordance with claim 5 in which there are provided means for counting the number of pulses of said train in 2N-1 pulse times of each recurrent period, such period having a duration of 2N pulse times, said counting means providing an N-bit output indication of its count, means for enabling operation of said indicating means during the last one of said pulse times of each period, binary rate multiplication means for converting at least a portion of said count indication into a further pulse train representing said delta modulated format, means responsive to said further pulse train for approximately reproducing said analog signal, and means responsive to an output of said indicating means in the last pulse time for modifying operation of the last-mentioned reproducing means for partially offsetting the signal reproducing effect of the last-mentioned pulse time.

Claim 10

The system in accordance with claim 5 in which means are provided for counting the number of pulses of said train in 2N-1 pulse times of each recurrent period, such period having a duration of 2N pulse times, said counting means providing an N-bit output indication of its count, means enable operation of said indicating means during the 2Nth one of said pulse times of each period, and means, responsive to an output of said indicating means, are provided for supplementing the output of said counting means with a new least significant bit indication corresponding to the state of said pulse train in said 2Nth phase and making a combined (N+1)-bit count indication.

Claim 11

The system in accordance with claim 7 in which binary rate multiplication means are provided for converting at least a portion of said (N+1)-bit count indication into a further pulse train representing said delta modulated format.

Claim 12

The combination in accordance with claim 7 in which register means are provided having N+1 storage bit positions, means apply the N least significant bits of said counting means output indication to the N most significant bit positions of said register means, and said supplementing means includes means coupling said new least significant bit indication to the least significant bit position of said register means.

Claim 13

The system in accordance with claim 5 in which said pulse train is supplied by means for receiving a differential pulse code modulated signal including successive binary code words, means for converting (M-a) most significant bits of each of said words into a pulse sequence corresponding to a portion of said delta modulated format, a being a real positive integer at least equal to one, and M being a real positive integer greater than or equal to a, and said indicating means comprising means, responsive to a least significant bits of each of said words, for actuating said periodic applying means.

Claim 14

The combination in accordance with claim 10 in which said circuit means includes integrating means comprising resistance means, capacitance means, and means connecting said resistance means and capacitance means in parallel, and means for applying said pulse train across such parallel connection.

Claim 15

The combination in accordance with claim 11 in which said resistance means comprises first and second resistors connected in series in the parallel connection with said capacitance means, and said offsetting means comprises means for coupling the output of said actuating means across said second resistor.

Claim 16

The combination in accordance with claim 11 in which a is equal to 2, and said coupling means comprises means for coupling across said second resistor a separate half-step of current of a polarity which is representative of the state of each of the two least significant bits, respectively, of each of said words.

Claim 17

The system in accordance with claim 5 in which said circuit means comprises electric current integrating means, and a bipolar current generator for supplying a fixed charge of one polarity or the other to said integrating means depending upon whether a pulse is present or absent, respectively, in each pulse time of said pulse train.

Claim 18

The system in accordance with claim 14 in which said current generator comprises a current source that is operative to either an ON or an OFF state depending upon whether or not a pulse is present in said train, and a current sink connected to both said source and said integrating means to draw current from said integrating means when said source is OFF.

Claim 19

The system in accordance with claim 14 in which said current generator comprises a pair of transistors of the same conductivity type, means connecting emitter electrodes of said transistors to a source of operating potential, means coupling to a base electrode of a first transistor of said pair to receive pulses of said pulse train for biasing said first transistor to a conducting state or a nonconducting state depending upon whether or not a pulse is present in each particular pulse time of said pulse train, means connecting a collector electrode of said first transistor to a first reference potential, means connecting a base electrode of a second transistor of said pair to a second reference potential having a potential level such that said second transistor conducts current in its emitter-collector path at a 2-current-unit leVel when said first transistor is in a nonconducting state and is nonconducting when said first transistor is in its conducting state, means for connecting the collector electrode of said second transistor to said integrating means, a third transistor of opposite conductivity type from said first and second transistors, means for connecting collector and emitter electrodes of said third transistor in series between a collector electrode of said second transistor and a third reference potential of lower potential magnitude than either of said first and second reference potentials, and means for connecting to a base electrode of said third transistor a fourth reference potential having a potential level such that said third transistor conducts in its collector-emitter path one unit of current from said integrating means when said first transistor is in its conducting state.

Claim 20

The combination in accordance with claim 16 wherein said current generator further comprises means receiving clock pulses at predetermined intervals, three control transistors for clocking said current generator to conduct current with respect to said integrating means only during said clock pulses, a first one of said control transistors being of the same conductivity type as said first and second transistors and having its emitter electrode connected to the emitter electrode of said second transistor and its collector electrode connected to said first reference potential, means applying said clock pulses to a base electrode of said first control transistor for biasing said such transistor into a conducting state except during each of said clock pulses, second and third ones of said control transistors each being of the same conductivity type as said third transistor and having their emitter electrodes connected to said emitter electrode of said third transistor and having their collector electrodes connected to said first reference potential, means for applying said pulse train to a base electrode of said second control transistor at a reduced voltage, and means applying said clock pulses, in inverted form, to a base electrode of said third control transistor at a reduced voltage.

Claim 21

The system in accordance with claim 16 in which said reference potentials and connecting means are proportioned to make a change of predetermined magnitude in charge in said integrating means over one of said pulse times.

Claim 22

In combination, a delta modulator for producing, in successive modulator sampling intervals, signals indicating the present nature of an input analog signal with respect to such analog signal in a prior sampling interval, said modulator including means responsive to said indicating signals for modifying modulator operation in steps of predetermined unit size, means for detecting the presence or absence of an indicating signal in at least one periodically recurring one of said sampling intervals, the recurrence period of said one interval being much greater than the recurrence period of said successive modulator sampling intervals, and means, responsive to an output of said detecting means, for effecting a change in the operation of said modifying means by a fixed portion of a unit step, and of one polarity or the other depending on whether said indicating signal was present or absent, and completing such change prior to the next succeeding recurrence of said one sampling interval.

Claim 23

In combination, a delta modulator for producing, in successive modulator sampling intervals, signals indicating the present nature of an input analog signal with respect to such analog signal in a prior sampling interval, said modulator including means responsive to said indicating signals for modifying modulator operation in steps of predetermined unit size, means for detecting the presence or absence of an indicating signal in at least one periodically recurring one of said sampling intervals, the recurrence period of said one interval being much greater than the recurrence period of said successive modulator sampling intervals, and means, responsive to an output of said detecting means, for effecting a change in the operation of said modifying means by a fixed portion of a unit step, and of one polarity or the other depending on whether said indicating signal was present or absent, and completing such change prior to the next succeeding recurrence of said one sampling interval.