Adder with fast detection of sum equal to zeroes or radix minus one

Claim 2

A logic system for determining a binary sum of all zeros which makes use of the half-sum (H), carry propagate (P) and carry generate (G) pulses of each bit position in said sum together with a low order input carry signal C in , comprising first logic circuit means for combining H and G pulses, second logic circuit means for combining H, P and C in pulses, and third logic circuit means for combining the outputs of said first and second logic circuit means and said input carry signal C in , said first, second and third logic circuit means connected to receive and combine pulse inputs according to ZEROES = (H.sub.0 + G.sub.1 + . . . G.sub.n.sub.-1 + C.sub.in) .sup.. (H.sub.0 + P.sub.1) . . . . (H.sub.n.sub.-2 + P.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 3

A logic system for detecting a binary sum of all zeroes which makes use of the half-sum (H) and carry propagate (P) pulses of each bit position in said sum together with a low order input carry signal C in and the high order output carry signal C out , comprising first logic circuit means for combining H, P and C in pulses, second logic circuit means for combining the outputs of said first logic circuit means with the C out signal, said first and second logic circuit means connected to receive and combine pulse inputs according to ZEROES = C.sub.out .sup.. (H.sub.0 + P.sub.1) .sup.. . . . ( H.sub.n.sub.-2 + P.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) + H.sub.0 .sup.. (H.sub.0 + P.sub.1) . . . . . (H.sub.n.sub.-2 + P.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 4

A logic system for detecting a binary sum of all zeroes which makes use of the half-sum (H) and carry propagate (P) pulses of each bit position in said sum together with a low order input carry signal C in and the high order output carry signal C out , comprising first logic circuit means for combining H, P and C in pulses, second logic circuit means for combining the outputs of said first logic circuit means with the C out signal, said first and second logic circuit means connected to receive and combine pulse inputs according to ZEROES = C.sub.out .sup.. (H.sub.0 + P.sub.1) .sup.. . . . ( H.sub.n.sub.-2 + P.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) + H.sub.0 .sup.. (H.sub.0 + P.sub.1) . . . . . (H.sub.n.sub.-2 + P.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 5

A logic system for detecting a binary sum of all zeroes which makes use of the half-sum (H), carry propagate (P) and carry generate (G) of each bit position in said sum together with a low order input carry signal C in and an intermediate order output carry signal C K , comprisng first logic circuit means for combining H and G pulses, second logic circuit means for combining the outputs of said first and second logic circuit means and said carry signal C K , said first, second and third logic circuit means connected to receive and combine inputs according to ZEROES = (H.sub.0 + G.sub.1 + . . . G.sub.K.sub.-1 + C.sub.K) .sup.. (H.sub.0 + P.sub.1) .sup.. (H.sub.1 + P.sub.2) . . . . . (H.sub.n.sub.-22 + P.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 6

A logic system for detecting a binary sum of all zeroes which makes use of the half-sum (H), carry propagate (P) and carry generate (G) of each bit position in said sum together with a low order input carry signal C in and an intermediate order output carry signal C K , comprisng first logic circuit means for combining H and G pulses, second logic circuit means for combining the outputs of said first and second logic circuit means and said carry signal C K , said first, second and third logic circuit means connected to receive and combine inputs according to ZEROES = (H.sub.0 + G.sub.1 + . . . G.sub.K.sub.-1 + C.sub.K) .sup.. (H.sub.0 + P.sub.1) .sup.. (H.sub.1 + P.sub.2) . . . . . (H.sub.n.sub.-22 + P.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 7

A logic system for detecting a sum of all zeroes where the addend and augend digits are numbers to the same radix r, first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend pair equal to the radix less one, and the third pulse indicative of a summation of the addend-augend pair equal to the radix, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pules of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to ZEROES = [(0).sub.o,r + (1).sub.r + . . . + (n-1).sub.r + C.sub.in ].sup.. [(0).sub.r.sub.-1 + (1).sub.0 ] . . . . . [n-2).sub.r.sub.-1 + (n-1).sub.0 ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum.

Claim 8

A logic system for detecting a sum of all zeroes where the addend and augend digits are numbers to the same radix r, first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend pair equal to the radix less one, and the third pulse indicative of a summation of the addend-augend pair equal to the radix, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pules of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to ZEROES = [(0).sub.o,r + (1).sub.r + . . . + (n-1).sub.r + C.sub.in ].sup.. [(0).sub.r.sub.-1 + (1).sub.0 ] . . . . . [n-2).sub.r.sub.-1 + (n-1).sub.0 ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum.

Claim 9

A logic system for detecting a decimal sum of all zeroes comprising first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend pair equal to nine, and the third pulse indicative of a summation of the addend-augend pair equal to ten, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said logic circuit means connected according to ZEROES = [(0).sub.0,10 + (1).sub.10 + . . . + (n-1).sub.10 + C.sub.in ] . [(0).sub.9 + (1).sub.0 ] . . . . . [(n-2).sub.9 + (n-1).sub.0 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit decimal sum.

Claim 10

A logic system for detecting a decimal sum of all zeroes comprising first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend pair equal to nine, and the third pulse indicative of a summation of the addend-augend pair equal to ten, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said logic circuit means connected according to ZEROES = [(0).sub.0,10 + (1).sub.10 + . . . + (n-1).sub.10 + C.sub.in ] . [(0).sub.9 + (1).sub.0 ] . . . . . [(n-2).sub.9 + (n-1).sub.0 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit decimal sum.

Claim 11

The logic system according to claim 5 where each decimal digit in said addend is represented in BCD form by four bit signals and where each augend digit is represented in BCD form by four bit signals, said bit signals indicating the quantities 8, 4, 2 and 1 respectively, wherein said first logic circuit means is comprised of a fifth logic circuit means for producing the carry propagate (P), and carry generate (G) pulses for each bit in the BCD summation, and a sixth logic circuit connected to said fifth circuit means for combining said G and P pulses to produce said first, second and third pulses.

Claim 12

The logic circuit of claim 5 where each decimal digit in said addend is represented in BCD form by four bit signals and where each augend digit is represented in BCD form by four bit signals, said bit signals indicating the quantities 8, 4, 2 and 1 respectively, said first logic circuit means comprising a fifth logic circuit means for producing the carry propagate (P) and carry generate (G) pulses for each bit in the BCD summation, a sixth logic circuit means connected to said fifth circuit means for combining said G and P pulses to produce a fourth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 12 at each digit position, a fifth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 10 at each digit position, and a sixth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 8 at each digit position, a seventh logic circuit means connected to said sixth logic circuit means for combining said fourth, fifth and sixth pulses together with the one order bits at each digit position to produce said second and third pulses.

Claim 13

A logic system for determining a binary sum of all ones which makes use of the half-sum (H), carry propagate (P) and carry generate (G) pulses of each bit position in said sum together with a low order input carry signal C in , comprising first logic circuit means for combining H and P pulses, second logic circuit means for combining H, G and C in pulses, and third logic circuit means for combining the outputs of said first and second logic circuit means and said input carry signal C in , said first, second and third logic circuit means connected to receive and combine pulse inputs according to ONES = (H.sub.0 + P.sub.1 + . . . + P.sub.n.sub.-1 +C.sub.in) .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 14

A logic system for determining a binary sum of all ones which makes use of the half-sum (H), carry propagate (P) and carry generate (G) pulses of each bit position in said sum together with a low order input carry signal C in , comprising first logic circuit means for combining H and P pulses, second logic circuit means for combining H, G and C in pulses, and third logic circuit means for combining the outputs of said first and second logic circuit means and said input carry signal C in , said first, second and third logic circuit means connected to receive and combine pulse inputs according to ONES = (H.sub.0 + P.sub.1 + . . . + P.sub.n.sub.-1 +C.sub.in) .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 15

A logic system for detecting a binary sum of all ones which makes use of the half-sum (H) and carry generate (G) pulses of each bit position in said sum together with a low order input carry signal C in and the high order output carry signal C out , comprising, first logic circuit means for combining H, G and C in pulses, second logic circuit means for combining the outputs of said first logic circuit means with the C out signal, said first and second logic circuit means connected to receive and combine; pulse inputs according to ONES = C.sub.out .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) + H.sub.0 .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 16

A logic system for detecting a binary sum of all ones which makes use of the half-sum (H) and carry generate (G) pulses of each bit position in said sum together with a low order input carry signal C in and the high order output carry signal C out , comprising, first logic circuit means for combining H, G and C in pulses, second logic circuit means for combining the outputs of said first logic circuit means with the C out signal, said first and second logic circuit means connected to receive and combine; pulse inputs according to ONES = C.sub.out .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) + H.sub.0 .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 17

A logic system for detecting a binary sum of all ones which makes use of the half-sum (H), carry propagate (P) and carry generate (G) pulses of each bit position in said sum together with a low order input carry signal C in , and an intermediate order output carry signal C K , comprising first logic circuit means for combining H and P pulses, second logic circuit means for combining H, G and C in pulses, and third logic circuit means for combining the outputs of said first and second logic circuit means and said carry signal C K , said first, second and third logic circuit means connected to receive and combine inputs according to ONES = (H.sub.0 + P.sub.1 + . . . + P.sub.K.sub.-1 + C.sub.K) .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 18

A logic system for detecting a binary sum of all ones which makes use of the half-sum (H), carry propagate (P) and carry generate (G) pulses of each bit position in said sum together with a low order input carry signal C in , and an intermediate order output carry signal C K , comprising first logic circuit means for combining H and P pulses, second logic circuit means for combining H, G and C in pulses, and third logic circuit means for combining the outputs of said first and second logic circuit means and said carry signal C K , said first, second and third logic circuit means connected to receive and combine inputs according to ONES = (H.sub.0 + P.sub.1 + . . . + P.sub.K.sub.-1 + C.sub.K) .sup.. (H.sub.0 + G.sub.1) . . . . . (H.sub.n.sub.-2 + G.sub.n.sub.-1) .sup.. (H.sub.n.sub.-1 + C.sub.in) where the subscripts 0 to n-1 refer to bit positions, high to low order, respectively, in an n-bit sum.

Claim 19

A logic system for detecting a sum where all digits are equal to the radix r less one where the addend and augend digits are numbers to the same said radix r, first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to 2(r-1), the second pulse indicative of a summation of the addend-augend pair equal to the radix less one, and the third pulse indicative of a summation of the addend-augend pair equal to the radix less two, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to SDRLO = [(0).sub.2(r.sub.-1) + (0).sub.r.sub.-2 + . . . + (n-1).sub.r.sub.-2 + C.sub.in ] .sup.. [(0).sub.r.sub.-1 + (1).sub.2(r.sub.-1) ] . . . . . [(n-2).sub.r.sub.-1 + (n-1).sub.2(r.sub.-1) ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum and where SDRLO stands for the summation of all digits equal to a radix less one.

Claim 20

A logic system for detecting a sum where all digits are equal to the radix r less one where the addend and augend digits are numbers to the same said radix r, first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to 2(r-1), the second pulse indicative of a summation of the addend-augend pair equal to the radix less one, and the third pulse indicative of a summation of the addend-augend pair equal to the radix less two, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to SDRLO = [(0).sub.2(r.sub.-1) + (0).sub.r.sub.-2 + . . . + (n-1).sub.r.sub.-2 + C.sub.in ] .sup.. [(0).sub.r.sub.-1 + (1).sub.2(r.sub.-1) ] . . . . . [(n-2).sub.r.sub.-1 + (n-1).sub.2(r.sub.-1) ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum and where SDRLO stands for the summation of all digits equal to a radix less one.

Claim 21

A logic system for detecting a decimal sum of all nines comprising first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to eighteen, the second pulse indicative of a summation of the addend-augend pair equal to nine, and the third pulse indicative of a summation of the addend-augend pair equal to eight, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said logic circuit means connected according to SDRLO = [(0).sub.18 + (0).sub.8 + . . . + (n-1).sub.8 + C.sub.in ] .sup.. [(0).sub.9 + (1).sub.18 ] . . . . . [(n-2).sub.9 + (n-1).sub.18 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n refers to the low order digit position in an n-digit decimal sum and where SDRLO stands for the summation of all digits equal to a radix less one.

Claim 22

A logic system for detecting a decimal sum of all nines comprising first logic circuit means for producing a set of three pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to eighteen, the second pulse indicative of a summation of the addend-augend pair equal to nine, and the third pulse indicative of a summation of the addend-augend pair equal to eight, second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said logic circuit means connected according to SDRLO = [(0).sub.18 + (0).sub.8 + . . . + (n-1).sub.8 + C.sub.in ] .sup.. [(0).sub.9 + (1).sub.18 ] . . . . . [(n-2).sub.9 + (n-1).sub.18 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n refers to the low order digit position in an n-digit decimal sum and where SDRLO stands for the summation of all digits equal to a radix less one.

Claim 23

The logic system according to claim 12 where each decimal digit in said addend is represented in BCD form by four bit signals and where each augend digit is represented in BCD form by four bit signals, said bit signals indicating the quantities 8, 4, 2 and 1 respectively, wherein said first logic circuit means is comprised of a fifth logic circuit means for producing the carry propagate (P) and carry generate (G) pulses for each bit in the BCD summation, and a sixth logic circuit connected to said fifth circuit means for combining said G and P pulses to produce said first, second and third pulses.

Claim 24

The logic circuit of claim 12 where each decimal digit in said addend is represented in BCD form by four bit signals and where each augend digit is represented in BCD form by four bit signals, said bit signals indicating the quantities 8, 4, 2 and 1 respectively, said first logic circuit means comprising a fifth logic circuit means for producing the carry propagate (P) and carry generate (G) pulses for each bit in the BCD summation, a sixth logic circuit means connected to said fifth circuit means for combining said G and P pulses to produce a fourth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 10 at each digit position, a fifth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 8 at each digit position, and a sixth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 6 at each digit position, and a seventh logic circuit means for combining said fourth, fifth and sixth pulses together with the one order bits at each digit position to produce said second and third pulses.

Claim 25

A logic system for detecting a sum where all digits are equal to zero and where all digits are equal to the radix less one, where the addend and augend digits are numbers to the radix r, first logic circuit means for producing a set of five pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend equal to the radix less one, the third pulse indicative of a summation of the addend-augend pair equal to the radix, a fourth pulse indicative of a summation of the addend-augend pair equal to the radix less two, and a fifth pulse indicative of a summation of the addend-augend pair equal to 2(r-1), second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to ZEROES = [(0).sub.o,r + (1).sub.r + . . . + (n-1).sub.r + C.sub.in ] .sup.. [(0).sub.r.sub.-1 + (1).sub.0 ] . . . . . [(n-2).sub.r.sub.-1 + (n-1).sub.0 ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum, fifth logic circuit means for combining said fifth pulse of the first digit position and said fourth pulse for each digit position together with said C in signal, sixth logic circuit means for combining said fifth and second pulses of the digit positions together with said C in , seventh logic circuit means for combining the outputs of said fifth and sixth logic circuit menas, said first, fifth, sixth and seventh logic circuit means connected according to SDRLO = [(0).sub.2(r.sub.-1) + (0).sub.r.sub.-2 + . . . + (n-1).sub.r.sub.-2 + C.sub.in ] .sup.. [(0).sub.r.sub.-1 + (1).sub.2(r.sub.-1) ] . . . . . [(n-2).sub.r.sub.-1 + (n-1).sub.2(r.sub.-1) ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum, and where SDRLO refers to the sum of the digits equal to the radix less one.

Claim 26

A logic system for detecting a sum where all digits are equal to zero and where all digits are equal to the radix less one, where the addend and augend digits are numbers to the radix r, first logic circuit means for producing a set of five pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend equal to the radix less one, the third pulse indicative of a summation of the addend-augend pair equal to the radix, a fourth pulse indicative of a summation of the addend-augend pair equal to the radix less two, and a fifth pulse indicative of a summation of the addend-augend pair equal to 2(r-1), second logic circuit means for combining said first pulse of the first digit position and said third pulse for each digit position together with a low order input carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to ZEROES = [(0).sub.o,r + (1).sub.r + . . . + (n-1).sub.r + C.sub.in ] .sup.. [(0).sub.r.sub.-1 + (1).sub.0 ] . . . . . [(n-2).sub.r.sub.-1 + (n-1).sub.0 ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum, fifth logic circuit means for combining said fifth pulse of the first digit position and said fourth pulse for each digit position together with said C in signal, sixth logic circuit means for combining said fifth and second pulses of the digit positions together with said C in , seventh logic circuit means for combining the outputs of said fifth and sixth logic circuit menas, said first, fifth, sixth and seventh logic circuit means connected according to SDRLO = [(0).sub.2(r.sub.-1) + (0).sub.r.sub.-2 + . . . + (n-1).sub.r.sub.-2 + C.sub.in ] .sup.. [(0).sub.r.sub.-1 + (1).sub.2(r.sub.-1) ] . . . . . [(n-2).sub.r.sub.-1 + (n-1).sub.2(r.sub.-1) ] .sup.. [(n-1).sub.r.sub.-1 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum, and where SDRLO refers to the sum of the digits equal to the radix less one.

Claim 27

A logic system for detecting a decimal sum where all the digits are equal to zero and where all the digits are equal to nines, comprising first logic circuit means for producing a set of five pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend pair equal to nine, the third pulse indicative of a summation of the addend-augend pair equal to 10, the fourth pulse indicative of a summation of the addend-augend pair equal to eight, and the fifth pulse indicative of a summation of the addend-augend pair equal to 18, second logic circuit means for combining said first pulse of the first digit position and third pulses for each digit position together with a low order carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to ZEROES = [(0).sub.0,10 + (1).sub.10 + . . . + (n-1).sub.10 + C.sub.in ] .sup.. [(0).sub.9 + (1).sub.0 ] . . . . . [(n-2).sub.9 + (n-1).sub.0 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum, fifth logic circuit means for combining said fifth pulse of the first digit position and fourth pulses for each digit position together with said signal C in , sixth logic circuit means for enabling said fifth and second pulses of the digit positions together with said signal C in , and seventh logic circuit means for combining the outputs of said fifth and sixth logic circuit means, said first, fifth, sixth and seventh logic circuit means connected according to NINES [(0).sub.18 + (0).sub.8 + . . . + (n-1).sub.8 + C.sub.in ] .sup.. [(0).sub.9 + (1).sub.18 ] . . . . . [(n-2).sub.9 + (n-1).sub.18 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum.

Claim 28

A logic system for detecting a decimal sum where all the digits are equal to zero and where all the digits are equal to nines, comprising first logic circuit means for producing a set of five pulses for each digit position in said sum, the first pulse indicative of a summation of the addend-augend pair equal to zero, the second pulse indicative of a summation of the addend-augend pair equal to nine, the third pulse indicative of a summation of the addend-augend pair equal to 10, the fourth pulse indicative of a summation of the addend-augend pair equal to eight, and the fifth pulse indicative of a summation of the addend-augend pair equal to 18, second logic circuit means for combining said first pulse of the first digit position and third pulses for each digit position together with a low order carry signal C in , third logic circuit means for combining said first and second pulses of the digit positions together with said signal C in , fourth logic circuit means for combining the outputs of said second and third logic circuit means, said four logic circuit means connected according to ZEROES = [(0).sub.0,10 + (1).sub.10 + . . . + (n-1).sub.10 + C.sub.in ] .sup.. [(0).sub.9 + (1).sub.0 ] . . . . . [(n-2).sub.9 + (n-1).sub.0 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum, fifth logic circuit means for combining said fifth pulse of the first digit position and fourth pulses for each digit position together with said signal C in , sixth logic circuit means for enabling said fifth and second pulses of the digit positions together with said signal C in , and seventh logic circuit means for combining the outputs of said fifth and sixth logic circuit means, said first, fifth, sixth and seventh logic circuit means connected according to NINES [(0).sub.18 + (0).sub.8 + . . . + (n-1).sub.8 + C.sub.in ] .sup.. [(0).sub.9 + (1).sub.18 ] . . . . . [(n-2).sub.9 + (n-1).sub.18 ] .sup.. [(n-1).sub.9 + C.sub.in ] where n-1 refers to the low order digit position in an n-digit sum.

Claim 29

The logic system according to claim 16 where each decimal digit in said sum is represented in BCD form by four bit signals and where each augend digit is represented in BCD form by four bit signals, said bit signals indicating the quantities 8, 4, 2 and 1 respectively, said first logic circuit means including an eighth logic circuit means for producing the carry propagate (P) and carry generate (G) pulses for each bit in the BCD summation and a ninth logic circuit means for combining said G and P pulses to produce said five pulses.

Claim 30

The logic circuit of claim 16 where each decimal digit in said addend is represented in BCD form by four bit signals and where each augend digit is represented in BCD form by four bit signals, said bit signals indicating the quantities 8, 4, 2 and 1 respectively, said first logic circuit means including an eighth logic circuit means for producing the carry propagate (P) and carry generate (G) pulses for each bit in the BCD summation, a ninth logic circuit means connected to said eighth logic circuit means for combining said G and P pulses to produce a sixth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 12 at each digit position, a seventh pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 10 at each digit position, an eighth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than 8 at each digit position, a ninth pulse indicative of a summation of the 8, 4 and 2 order bits equal to or greater than six at each digit position, and a tenth logic circuit means for combining said sixth, seventh, eighth and ninth pulses together with the one order bits at each digit position to produce said second, third and fourth pulses.