US3629565A
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US
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Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
Assignee: International Business Machines Corp
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Filing: 1970-02-13
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Granted: 1971-12-21
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Expires: 1990-02-13
Abstract
Abstract An improved method and logic system for adding two decimal numbers which are coded in a four-bit binary form. The method includes generating a propagate carry signal Pi for each of the four bits which is the OR function of the bit inputs, generating a generate carry signal Gi for each of the four bits which is the AND function of the bit inputs, and generating a binary carry C1 for the first bit. The decimal carry for the addition is then generated by a novel carry look-ahead technique by employing these signals: Pi, Gi, and the binary carry C1. The binary coded decimal bit signals representative of the decimal sum are also generated directly from these signals and, hence, the adder differs from prior art decimal adders which first performed binary addition in each bit and then added 6 to these binary sums whenever a decimal carry occurred so as to produce corrected binary signals representative of the coded decimal number. Several systems are disclosed employing this method and include a four-logic level, two-digit decimal adder, a three-logic level, two-digit decimal adder; and a six-logic level, eight-digit decimal adder. The six-logic level, eight-digit decimal adder combines concepts of the disclosed novel method for implementing decimal carries, as well as conventional group carry techniques used in parallel binary adders.
Inventors
- 👤 Martin S Schmookler
- 👤 Arnold Weinberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 03:04
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/492; G06F7/493; G06F7/494; G06F2207/00; G06F2207/492; G06F2207/4924
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
210 words
A method for performing decimal addition in a logic system including a plurality of logic circuits, wherein the augend and the addend each are represented in a four-bit binary code and said logic system has a low-order input carry signal Cin, comprising: a. logically producing a propagate signal Pi for each bit of said binary coded inputs where Pi Ai+Bi and Ai and Bi are the binary coded bit values of the augend and addend, respectively, of any bit i of the four bits; b. logically producing a generate signal Gi for each bit i of said binary coded inputs where Gi AiBi; c. logically producing a binary carry signal C1 from the input values comprising the first bit of said binary coded bit values and said input carry signal where C1 G1+P1Cin; d. logically producing a decimal carry signal for said decimal addition from said propagate signals, said generate signals, and said binary carry of the first bit; and e. generating binary signals representative of the decimal Sum of said augend and addend from said propagate signals, said generate signals, and said decimal carry signal, whereby the said decimal sum is represented at the output of said logic system for by four-bit coded signals and said decimal carry signal.
Claim 2
Independent Claim
210 words
A method for performing decimal addition in a logic system including a plurality of logic circuits, wherein the augend and the addend each are represented in a four-bit binary code and said logic system has a low-order input carry signal Cin, comprising: a. logically producing a propagate signal Pi for each bit of said binary coded inputs where Pi Ai+Bi and Ai and Bi are the binary coded bit values of the augend and addend, respectively, of any bit i of the four bits; b. logically producing a generate signal Gi for each bit i of said binary coded inputs where Gi AiBi; c. logically producing a binary carry signal C1 from the input values comprising the first bit of said binary coded bit values and said input carry signal where C1 G1+P1Cin; d. logically producing a decimal carry signal for said decimal addition from said propagate signals, said generate signals, and said binary carry of the first bit; and e. generating binary signals representative of the decimal Sum of said augend and addend from said propagate signals, said generate signals, and said decimal carry signal, whereby the said decimal sum is represented at the output of said logic system for by four-bit coded signals and said decimal carry signal.
Claim 3
Dependent Claim
45 words
The method of claim 1 wherein said step for producing said decimal carry signal comprises logically solving the equation Cd K+LC1, or its logical equivalent where Cd is said decimal carry, C1 is said binary carry of the first bit, K G8+P8P4+P8P2+G4P2, and L P8+G4+P4G2.
Claim 4
Dependent Claim
32 words
The method of claim 1 wherein said step of generating binary signals representative of the decimal sum includes the step of generating a half-sum signal Hi for each bit where Hi AiBi+AiBi.
Claim 5
Dependent Claim
132 words
The method of claim 3 wherein said step for generating binary signals representative of the decimal sum further comprises logically solving the following equations or their logical equivalents: a. S1 (H1+Cin)Cin+P1C1 where S1 is the binary coded output signal for the first bit; b. S2 H2C1Cd+H2C1Cd+H2C1Cd+H2C1Cd or S2 H2LC1+H2LC1+H2KC1+H2KC1 where S2 is the binary coded output signal K G8+P8P4+G4P2, and L P8+G4+P4G2 for the second bit; c. S4 P4G2+P8H4P2+P8H4(P4+G2)P2C1+P8H4C1+(H4H2+G8)C1 or S4 P8G4(P4+P2)(P4+G2)+P8P4P2C1+G4G2C1+P8P4C1+(G8+H2)(G8+H4)C1 where S4 is the binary coded output signal for the third bit; d. S8 H8(H4H2+G8)C1+LCd or S8 H8(H4H2+G8)C1+LKC1 where S8 is the binary coded output signal for the fourth bit; whereby, S1, S2, S4, and S8 represent the sum of the decimal addition in said four-bit binary code and Cd represents the decimal carry signal emanating from this decimal digit.
Claim 6
Dependent Claim
210 words
A logic system for preforming decimal addition, wherein an augend and an addend each are represented in a four-bit binary code and said logic system receives a low-order input carry signal Cin, comprising: a. logic means for implementing a propagate signal Pi for each bit of said binary coded inputs where Pi Ai+Bi and Ai and Bi are the binary coded bit values of the augend and addend, respectively, of any bit i of the four bits; b. logic means for implementing a generate signal Gi for each bit i of said binary coded inputs where Gi AiBi; c. logic means for implementing a binary carry signal C1 from the input values comprising the first bits of said binary coded bit values and said input carry signals where C1 G1+P1Cin; d. logiC means for implementing the decimal carry signal for said decimal addition from said propagate signals, said generated signals, said binary carry of the first bit; and e. logic means for generating binary signals representative of the decimal sum of said augend and addend from said propagate signals, said generate signals, and said decimal carry signal, whereby said decimal sum is represented at the output of said logic system by four-bit binary coded signals and said decimal carry signal.
Claim 7
Dependent Claim
210 words
A logic system for preforming decimal addition, wherein an augend and an addend each are represented in a four-bit binary code and said logic system receives a low-order input carry signal Cin, comprising: a. logic means for implementing a propagate signal Pi for each bit of said binary coded inputs where Pi Ai+Bi and Ai and Bi are the binary coded bit values of the augend and addend, respectively, of any bit i of the four bits; b. logic means for implementing a generate signal Gi for each bit i of said binary coded inputs where Gi AiBi; c. logic means for implementing a binary carry signal C1 from the input values comprising the first bits of said binary coded bit values and said input carry signals where C1 G1+P1Cin; d. logiC means for implementing the decimal carry signal for said decimal addition from said propagate signals, said generated signals, said binary carry of the first bit; and e. logic means for generating binary signals representative of the decimal sum of said augend and addend from said propagate signals, said generate signals, and said decimal carry signal, whereby said decimal sum is represented at the output of said logic system by four-bit binary coded signals and said decimal carry signal.
Claim 8
Dependent Claim
49 words
The logic system of claim 5 wherein said means for implementing said decimal carry signal comprises means to logically solve the equation Cd K+LC1 or its logical equivalent, where Cd is said decimal carry signal, C1 is said binary carry from the first bit, K G8+P8P4+P8P2+G4P2, and L P8+G4+P4G2.
Claim 9
Dependent Claim
33 words
The logic system of claim 5 wherein said logic means for generating binary signals representative of the decimal sum includes means for generating a half-sum signal Hi for each bit where Hi AiBi+AiBi.
References Cited (Backward Citations)
US3308284A
Cited
US3304418A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-20 | 1975-06-21 | 1975-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-20 | 1979-06-21 | 1979-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-20 | 1983-06-21 | 1983-12-21 | $7700.00 | Window Closed / Lapsed |