Qui-binary adder and readout latch

Claim 1

A QUI-BINARY ADDER AND READOUT CIRCUIT COMPRISING: (A) FIRST AND SECOND SETS OF INPUT LINES PROVIDING FIRST AND SECOND SETS OF CONCURRENT SIGNALS REPRESENTING THE DECIMAL DIGITS IN ACCORDANCE WITH A NORMAL NUMBERING SYSTEM, (B) A TRANSLATING MEANS INCLUDING A PLURALITY OF AND AND OR SWITCH CIRCUIT CONFIGURATIONS FOR CONVERTING THE SIGNALS ON SAID FIRST AND SECOND SETS OF INPUT LINES FROM BINAR CODED DECIMAL TO QUI-BINARY NOTATION, (C) AN ADDER MATRIX INCLUDING CAPACTIVE ELEMENTS FOR SELECTIVELY COUPLING THE OUTPUTS OF SAID AND AND OR SWITCH CIRCUITS FOR DERIVING SUM REPRESENTING SIGNALS, AND (D) A SET OF SUM OUTPUT LINES EACH INCLUDING A LATCH CIRCUIT ADAPTED TO RESPOND TO THE SUM REPRESENTING SIGNALS FROM SAID ADDER MATRIX.