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US3961355A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming

Assignee: International Business Machines Corp
•
Filing: 1974-11-18
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Granted: 1976-06-01
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Expires: 1994-11-18
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Abstract

Abstract A semiconductor device has a heavily doped semiconductor substrate with a lightly doped epitaxial layer overlying a surface of the substrate and of the same conductivity type as the substrate. Electrically insulating barriers extend from at least the surface of the epitaxial layer into the substrate so as to electrically isolate non-common areas of each surface leakage sensitive device within the epitaxial layer from the non-common areas of adjacent surface leakage sensitive devices.

Inventors

  • 👤 Shakir A. Abbas
  • 👤 Chi S. Chang
  • 👤 Leo B. Freeman, Jr.
  • 👤 Ronald W. Knepper

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 15:10
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10B; H10B12/00; H10B12/30; H10W10/10; H10W10/13; H10W20/00; H10W20/20

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 265 words
A semiconductor device comprising: a heavily doped semiconductor substrate; a lightly doped epitaxial layer overlying a surface of said substrate and having the same conductivity type as said substrate; an electrically insulating layer disposed on the surface of said epitaxial layer at selected locations and comprising a separate portion at each location; said epitaxial layer having a surface leakage sensitive device therein beneath each separated portion of said insulating layer; a plurality of electrically insulating barriers extending from the surface of said epitaxial layer through said epitaxial layer and into said substrate to electrically isolate surface leakage sensitive areas of said devices from each other; said insulating barriers having a depth greater than the depth of said insulating layer, the depth of said insulating barriers being at least as great as that of said epitaxial layer; a highly doped diffusion of opposite conductivity type to said substrate and said epitaxial layer disposed in said epitaxial layer and in contact with said insulating barriers; each of said insulating barriers extending into said substrate for a distance less than the thickness of said substrate and laterally surrounding each said surface leakage sensitive device except where each said barrier is discontinuous to allow a conductive path between said diffusion and a respective one of said surface leakage sensitive devices; said conductive path comprising the entire thickness of said epitaxial layer said diffusion and each of said surface leakage sensitive devices being located on opposite sides of said discontinuous barriers; and each said conductive path constituting a component part of a respective one of said surface leakage sensitive devices.
Claim 2
Dependent Claim 265 words
A semiconductor device comprising: a heavily doped semiconductor substrate; a lightly doped epitaxial layer overlying a surface of said substrate and having the same conductivity type as said substrate; an electrically insulating layer disposed on the surface of said epitaxial layer at selected locations and comprising a separate portion at each location; said epitaxial layer having a surface leakage sensitive device therein beneath each separated portion of said insulating layer; a plurality of electrically insulating barriers extending from the surface of said epitaxial layer through said epitaxial layer and into said substrate to electrically isolate surface leakage sensitive areas of said devices from each other; said insulating barriers having a depth greater than the depth of said insulating layer, the depth of said insulating barriers being at least as great as that of said epitaxial layer; a highly doped diffusion of opposite conductivity type to said substrate and said epitaxial layer disposed in said epitaxial layer and in contact with said insulating barriers; each of said insulating barriers extending into said substrate for a distance less than the thickness of said substrate and laterally surrounding each said surface leakage sensitive device except where each said barrier is discontinuous to allow a conductive path between said diffusion and a respective one of said surface leakage sensitive devices; said conductive path comprising the entire thickness of said epitaxial layer said diffusion and each of said surface leakage sensitive devices being located on opposite sides of said discontinuous barriers; and each said conductive path constituting a component part of a respective one of said surface leakage sensitive devices.
Claim 3
Dependent Claim 17 words
The semiconductor device according to claim 1 in which said insulating barriers are formed of silicon dioxide.
Claim 4
Dependent Claim 29 words
The semiconductor device according to claim 1 in which each said surface leakage sensitive device includes a field effect transistor and each said conductive path constitutes the channel thereof.
Claim 5
Dependent Claim 14 words
The semiconductor device according to claim 1 in which said substrate is monocrystalline silicon.
Claim 6
Dependent Claim 43 words
The semiconductor device according to claim 4 in which: said substrate has a thickness several times the thickness of said epitaxial layer; and each of said insulating barriers extends into said substrate for a thickness less than the thickness of said epitaxial layer.
Claim 7
Dependent Claim 63 words
The semiconductor device according to claim 1 in which said insulating barrier extends above the surface of said epitaxial layer in any area in which said insulating layer is disposed on the surface of said epitaxial layer and extends to the surface of said epitaxial layer in all other areas to separate each of said portions of said insulating layer from adjacent portions.

References Cited (Backward Citations)

US3354360A Cited
US3492174A Cited
US3786318A Cited
US3509433A Cited
US3648125A Cited
US3783047A Cited
US3906544A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-06-01 1979-12-01 1980-06-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-06-01 1983-12-01 1984-06-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-06-01 1987-12-01 1988-06-01 $7700.00 Window Closed / Lapsed

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