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US3948694A
Expired / Lapsed
US
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Self-aligned method for integrated circuit manufacture
Assignee: Motorola Solutions Inc
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Filing: 1975-04-30
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Granted: 1976-04-06
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Expires: 1995-04-30
Abstract
Abstract A method for manufacturing integrated circuits provides total self-alignment of all critically positioned device regions. Self-alignment is accomplished by a combination of selectively etchable thin layers on the surface of a semiconductor body. An initially formed predetermined pattern of openings defines all active regions of the device. Selective introduction of impurities in sub-sets of this predetermined pattern form regions of a semiconductor device in a totally self-aligned manner while ion implantation through all overlying layers provides for the formation of further shallow device regions irrespective of the predetermined pattern of openings.
Inventors
- 👤 B. David Mills, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:02
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/085; Y10S148/106
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
A self-aligned method of manufacturing integrated circuits comprising the steps of: a. providing a buried layer and an upper layer over a semiconductor substrate, said upper layer and said substrate being of a first conductivity type, and said buried layer being of a second conductivity type opposite to said first conductivity type; b. forming a single masking means over the upper surface of said upper layer, said single mask means having a predetermined pattern of openings formed therein; c. forming a semiconductor device by applying impurities through said predetermined pattern of openings formed in said forming step and by applying impurities through portions of said masking means not constituted by said predetermined pattern of openings.
Claim 2
Dependent Claim
115 words
A self-aligned method of manufacturing integrated circuits comprising the steps of: a. providing a buried layer and an upper layer over a semiconductor substrate, said upper layer and said substrate being of a first conductivity type, and said buried layer being of a second conductivity type opposite to said first conductivity type; b. forming a single masking means over the upper surface of said upper layer, said single mask means having a predetermined pattern of openings formed therein; c. forming a semiconductor device by applying impurities through said predetermined pattern of openings formed in said forming step and by applying impurities through portions of said masking means not constituted by said predetermined pattern of openings.
Claim 3
Dependent Claim
101 words
A self-aligned method of manufacturing integrated circuits comprising the steps of: a. providing a semiconductor substrate of a first conductivity, said semiconductor substrate having an overlying layer of a second conductivity; b. depositing a single masking means over the upper surface of said overlying layer, said single masking means having a predetermined pattern of openings formed therein; c. forming regions of a semiconductor device by applying impurities through said predetermined openings; d. forming a further shallow device region, encompassing said device regions formed by applying impurities through said predetermined openings, said shallow device region being formed irrespective of said predetermined openings.
Claim 4
Dependent Claim
101 words
A self-aligned method of manufacturing integrated circuits comprising the steps of: a. providing a semiconductor substrate of a first conductivity, said semiconductor substrate having an overlying layer of a second conductivity; b. depositing a single masking means over the upper surface of said overlying layer, said single masking means having a predetermined pattern of openings formed therein; c. forming regions of a semiconductor device by applying impurities through said predetermined openings; d. forming a further shallow device region, encompassing said device regions formed by applying impurities through said predetermined openings, said shallow device region being formed irrespective of said predetermined openings.
Claim 5
Dependent Claim
30 words
The self-aligned method of manufacturing integrated circuits recited in claim 2 wherein said single masking means comprises at least two layers which are selectively etchable with respect to each other.
Claim 6
Dependent Claim
22 words
The self-aligned method of manufacturing integrated circuits as recited in claim 3 wherein at least one of said layers is silicon dioxide.
Claim 7
Dependent Claim
24 words
The self-aligned method of manufacturing integrated circuits as recited in claim 3 wherein at least one of said selectively etchable layers is silicon nitride.
Claim 8
Dependent Claim
21 words
The self-aligned method of manufacturing integrated circuits recited in claim 2 wherein said upper layer is an epitaxially deposited silicon layer.
Claim 9
Dependent Claim
17 words
The self-aligned method of manufacturing integrated circuits recited in claim 2 wherein said semiconductor substrate is silicon.
Claim 10
Dependent Claim
37 words
The self-aligned method of manufacturing integrated circuits recited in claim 2 wherein said device regions formed by applying impurities through said predetermined pattern of openings comprise the collector region, base region, and emitter region of a transistor.
Claim 11
Dependent Claim
225 words
A self-aligned method of manufacturing integrated circuits comprising the steps of: a. providing a buried layer and upper layer over a semiconductor substrate, said upper layer and said substrate being of a first conductivity type and said buried layer being of a second conductivity type opposite to said first conductivity type; b. depositing a first masking layer over the upper surface of said upper layer; c. depositing a second masking layer over the upper surface of said first masking layer; d. forming a predetermined pattern of openings in said second layer, said predetermined pattern comprising a first, a second, and a third group of openings; e. forming a first group of semiconductor device regions by applying impurities through openings etched through said first masking layer using said first group of openings as an etching mask; f. forming a second group of semiconductor device regions by applying impurities through openings etched through said first masking layer using said second group of openings as an etching mask; g. forming a shallow device region, said shallow device region overlaying the upper surfaces of said first and said second group of device region and said shallow device region being formed irrespective of said predetermined pattern of openings; h. forming a group of contact openings through said first masking layer using said third group of openings as an etching mask.
Claim 12
Dependent Claim
225 words
A self-aligned method of manufacturing integrated circuits comprising the steps of: a. providing a buried layer and upper layer over a semiconductor substrate, said upper layer and said substrate being of a first conductivity type and said buried layer being of a second conductivity type opposite to said first conductivity type; b. depositing a first masking layer over the upper surface of said upper layer; c. depositing a second masking layer over the upper surface of said first masking layer; d. forming a predetermined pattern of openings in said second layer, said predetermined pattern comprising a first, a second, and a third group of openings; e. forming a first group of semiconductor device regions by applying impurities through openings etched through said first masking layer using said first group of openings as an etching mask; f. forming a second group of semiconductor device regions by applying impurities through openings etched through said first masking layer using said second group of openings as an etching mask; g. forming a shallow device region, said shallow device region overlaying the upper surfaces of said first and said second group of device region and said shallow device region being formed irrespective of said predetermined pattern of openings; h. forming a group of contact openings through said first masking layer using said third group of openings as an etching mask.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-04-06 | 1979-10-06 | 1980-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-04-06 | 1983-10-06 | 1984-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-04-06 | 1987-10-06 | 1988-04-06 | $7700.00 | Window Closed / Lapsed |