Charge coupled device multiplexer

Claim 2

A charge coupled device analog signal multiplexer which comprises: a. a charge coupled device shift register characterized by an array of sets of phase electrodes, b. a plurality of charge packet injection input channels, each including means for providing charge packet inputs representative of time samples of respective analog signal inputs at an electrode location only in a pre-selected number of said phase electrode sets less than the total number of said sets, the remainder of said sets defining isolation electrode sets disposed between said pre-selected electrode sets to provide isolation sets not connected to any signal input means, c. a transfer gate common to all of said charge packet input means to admit said charge packets to said array, d. clock means to apply shift voltages to said array to move said charge packets to the multiplexer output, and e. detector means to detect said charge packets at said output.

Claim 3

The combination set forth in claim 1 in which: a. a pair of said arrays are provided, b. said detector means is connected to the outputs of both said arrays, and c. said charge packet injection channels are connected to sets in one of said arrays separated from said detector means by an odd number of sets and connected to sets in the other of said arrays separated from said detector means by an even number of sets.

Claim 4

The combination set forth in claim 2 wherein each of said preselected sets comprises three electrodes and wherein one three electrode isolation set is positioned between each of said preselected sets.

Claim 5

The combination set forth in claim 1 wherein each of said preselected sets comprises three electrodes and wherein one three electrode isolation set is positioned between each of said preselected sets.

Claim 6

The combination set forth in claim 1 wherein said charge coupled device shift register has said array of phase electrodes supported on an insulating layer on a semiconductor substrate with channel stop regions extending the length of said array and on opposite sides thereof and wherein one of said channel stop regions has a plurality of bays leading by way of inlet channels from the section of said semiconductor substrate between said channel stop regions and wherein said means for providing charge packet inputs comprises a diode in each of said bays.

Claim 7

The combination set forth in claim 1 in which said CCD shift register is a surface channel device.

Claim 8

The combination set forth in claim 1 wherein each said set comprises three side-by-side electrodes.

Claim 9

A charge coupled device analog signal multiplexer which comprises: a. a charge coupled device shift register characterized by an array of sets of phase electrodes, b. a plurality of charge packet injection input channels each including means for providing charge packet inputs representative of time samples of respective analog signal inputs at an electrode location only in a preselected number of said phase electrode sets less than the total number of said sets, the remainder of said sets defining isolation electrode sets disposed between said preselected electrode sets, c. a transfer gate common to all of said charge packet input means to admit said charge packets to said array, d. clock means to apply shift voltages to said array to shift said charge packets to the multiplexer output, and e. detector means for detecting said charge packets at said output and for summing each charge packet with the charge associated with its trailing isolation charge packet.

Claim 10

A charge coupled device analog signal multiplexer which comprises: a. a charge coupled device shift register characterized by an array of sets of phase electrodes, b. a plurality of charge packet injection input channels each including means for providing charge packet inputs representative of time samples of respective analog signal inputs at an electrode location only in a preselected number of said phase electrode sets less than the total number of said sets, the remainder of said sets defining isolation electrode sets disposed between said preselected electrode sets, c. a transfer gate common to all of said charge packet input means to admit said charge packets to said array, d. clock means to apply shift voltages to said array to shift said charge packets to the multiplexer output, and e. detector means for detecting said charge packets at said output and for summing each charge packet with the charge associated with its trailing isolation charge packet.

Claim 13

A method according to claim 9, wherein said charge packet inputs are injected only at alternate phase electrode set locations along said shift register.

Claim 14

A method according to claim 10, wherein each charge packet detected at said output during one period of said clock signals is summed with a charge packet detected at said output during the next following period of said clock signals.

Claim 15

A charge coupled device analog signal multiplexer which comprises: a. a semiconductor substrate on which an insulating layer supports an array of sets of side-by-side phase electrodes and in which channel stop regions are provided, forming a charge coupled device shift register structure, b. a plurality of diode means located in bays in said channel stop regions having inlet channels leading only beneath preselected elements in pre-determined ones of said sets less than the total number of said sets to inject charge packets into said structure representative of time samples of respective analog signal inputs to said channels, the remainder of the said electrode sets defining isolation sets located between said preselected sets and offset from said inlet channels in said channel stop regions, said isolation sets not being connected to any signal input means, c. connections to apply different voltages to members of said sets to shift said charge packets along said array; and d. detecting means in said structure to detect charge packets arriving at the end of said array.

Claim 16

A charge coupled device analog signal multiplexer which comprises: a. a semiconductor substrate on which an insulating layer supports an array of sets of side-by-side phase electrodes and in which channel stop regions are provided, forming a charge coupled device shift register structure, b. a plurality of diode means located in bays in said channel stop regions having inlet channels leading only beneath preselected elements in pre-determined ones of said sets less than the total number of said sets to inject charge packets into said structure representative of time samples of respective analog signal inputs to said channels, the remainder of the said electrode sets defining isolation sets located between said preselected sets and offset from said inlet channels in said channel stop regions, said isolation sets not being connected to any signal input means, c. connections to apply different voltages to members of said sets to shift said charge packets along said array; and d. detecting means in said structure to detect charge packets arriving at the end of said array.

Claim 17

The combination set forth in claim 12 in which said bays and inlets are formed in a channel stop region extending along one boundary of said array.

Claim 18

The combination set forth in claim 12 in which each of said inlets is narrower than and underlies an end of one of said electrodes.

Claim 19

The combination set forth in claim 14 in which a transfer gate electrode on said insulating layer extends the length of said array and overlays said inlet channels and is spaced from the ends of said electrodes.

Claim 20

The combination set forth in claim 14 in which: a. channel stop regions define a plurality of channels in said substrate, b. different electrode arrays span each of said channels to form a plurality of shift register structures, and c. said detector means is connected to the outputs of said structures with input connections through said diode means to regularly spaced elements of one said array beginning with the set adjacent to said detector means and with input connections through said diode means to regularly spaced elements of the other said arrays beginning with sets spaced by regularly increasing number of said sets from said detector means.

Claim 21

The combination set forth in claim 16 in which only two channels are defined on a substrate.

Claim 22

In an analog signal time division multiplexer which comprises a plurality of signal input channels, each channel including means for providing time varying analog input signals, the combination comprising: a. a semiconductor substrate on which there is formed an insulating layer which supports a plurality of sets of side-by-side phase electrodes and in which channel stop regions are provided to form a charge coupled device shift register structure, b. a plurality of diode means located in bays in said channel stop regions having inlet channels corresponding with respective ones of said signal channels, said inlet channels leading only beneath pre-selected ones of said electrode sets to inject charge packets into said structure, said plurality of electrode sets including further electrode sets disposed between said pre-selected sets to provide isolation sets not connected with any signal input means, and connections to apply different voltages to members of said electrode sets to shift said charge packets along said shift register structure, and c. means in said structure to detect charge packets arriving at the output of said shift register structure.

Claim 23

In an analog signal time division multiplexer which comprises a plurality of signal input channels, each channel including means for providing time varying analog input signals, the combination comprising: a. a semiconductor substrate on which there is formed an insulating layer which supports a plurality of sets of side-by-side phase electrodes and in which channel stop regions are provided to form a charge coupled device shift register structure, b. a plurality of diode means located in bays in said channel stop regions having inlet channels corresponding with respective ones of said signal channels, said inlet channels leading only beneath pre-selected ones of said electrode sets to inject charge packets into said structure, said plurality of electrode sets including further electrode sets disposed between said pre-selected sets to provide isolation sets not connected with any signal input means, and connections to apply different voltages to members of said electrode sets to shift said charge packets along said shift register structure, and c. means in said structure to detect charge packets arriving at the output of said shift register structure.

Claim 24

In an analog signal time division multiplex system comprising a plurality of signal input channels, each channel including means for providing time varying analog input signals, a charge coupled device shift register structure including: a. a multi-set array of phase electrodes; b. a plurality of means connected with each said input channel for providing charge packet inputs representative of time samples of analog signal inputs on said respective input channels at an electrode location only in pre-selected electrode sets in said array, said array including further electrode sets disposed between said pre-selected sets and not connected with any charge packet input means; c. transfer gate means common to all of said charge packet input means to admit charge packets therefrom into said shift register only at said pre-selected electrode set locations; d. means for clocking along said array charge packets introduced from said input means; and e. means to detect the charge packets at the end of said array for producing a multiplexed analog signal output.

Claim 25

In an analog signal time division multiplex system comprising a plurality of signal input channels, each channel including means for providing time varying analog input signals, a charge coupled device shift register structure including: a. a multi-set array of phase electrodes; b. a plurality of means connected with each said input channel for providing charge packet inputs representative of time samples of analog signal inputs on said respective input channels at an electrode location only in pre-selected electrode sets in said array, said array including further electrode sets disposed between said pre-selected sets and not connected with any charge packet input means; c. transfer gate means common to all of said charge packet input means to admit charge packets therefrom into said shift register only at said pre-selected electrode set locations; d. means for clocking along said array charge packets introduced from said input means; and e. means to detect the charge packets at the end of said array for producing a multiplexed analog signal output.

Claim 26

A charge coupled device analog signal multiplexer which comprises: a. a charge coupled device shift register including a first array of phase electrode set means and a plurality of charge packet injection input channels each including means for providing charge packet inputs representative of time samples of respective analog signal inputs at an electrode location in each of said phase electrode set means of said first array; b. transfer gate means common to all of said charge packet input means to admit said charge packets to said first array; c. disposed between electrode set means of said first array a second array of phase electrode set means for receiving charge packets derived from time samples of respective analog signal inputs only from an adjacent electrode set means of said first array; d. clock means to apply shift voltages to said first and second arrays to move said charge packets to the multiplexer output, and e. detector means to detect said charge packets at said output.

Claim 27

A charge coupled device analog signal multiplexer which comprises: a. a charge coupled device shift register including a first array of phase electrode set means and a plurality of charge packet injection input channels each including means for providing charge packet inputs representative of time samples of respective analog signal inputs at an electrode location in each of said phase electrode set means of said first array; b. transfer gate means common to all of said charge packet input means to admit said charge packets to said first array; c. disposed between electrode set means of said first array a second array of phase electrode set means for receiving charge packets derived from time samples of respective analog signal inputs only from an adjacent electrode set means of said first array; d. clock means to apply shift voltages to said first and second arrays to move said charge packets to the multiplexer output, and e. detector means to detect said charge packets at said output.