Drive circuitry with error detection

Claim 2

Apparatus for transmitting signals along a plurality of paths and for determining whether or not signals are being transmitted on a predetermined number of the paths, said apparatus including in combination a plurality of signal paths; a resistance network comprising an equal plurality of resistances, each resistance having one end connected to a different one of said signal paths and the other end connected to a common juncture, the voltage level produced at the common juncture being proportional to the number of signal paths having signals present thereon; first detecting means coupled to said common juncture and operable to produce a first indication in response to a voltage level at said common juncture produced by a predetermined number (N) or more signal paths having signals present thereon during a detection period, and operable to produce a second indication in response to a voltage level at said common juncture produced by less than the predetermined number (N) of signal paths having signals present thereon during a detection period; second detecting means coupled to said common juncture and operable to produce a first indication in response to a voltage level at said common juncture produced by less than said predetermined number plus one (N+1) signal paths having signals present thereon, and operable to produce a second indication in response to a voltage level at said common juncture produced by said predetermined number plus one (N+1) or more signal paths having signals present thereon; and output means coupled to said first and second detecting means for producing an error signal in response to a second indication from the first detecting means or from the second detecting means.

Claim 3

Apparatus in accordance with claim 1 including enabling means for producing an enabling signal in response to predetermined input conditions being applied thereto; said first detecting means being coupled to said enabling means, said first detecting means being operable to produce said first indication when said predetermined number (N) or more signal paths have signals present thereon during an enabling signal and being operable to produce said second indication when less than the predetermined number (N) of signal paths have signals present thereon during an enabling signal.

Claim 4

Apparatus in accordance with claim 2 including activating means for activating said signal paths to permit the passage of signals therealong; and control means coupled to said activating means for preventing said activating means from activating said signal paths in the absence of said predetermined input conditions being applied thereto.

Claim 5

Apparatus in accordance with claim 3 wherein each of said plurality of signal paths includes an input terminal adapted to receive input signal data, an output terminal, and a driving means connected between said input and output terminals for producing a driving voltage at the output terminal in response to input signal data at the input terminal; said activating means is coupled to said driving means of the plurality of signal paths and is operable to activate said signal paths by applying operating potentials to said driving means; and said one end of each of said resistances is connected to the output terminal of its associated signal path.

Claim 6

Apparatus in accordance with claim 4 wherein said first detecting means includes a first comparator means having one input connected to said common juncture and another input connected to a first point of reference potential, said first comparator means being operable to produce a first output signal when the voltage at the common juncture is that produced by less than the predetermined number (N) of signal paths having signals present thereon, and to produce a second output signal when the voltage at the common juncture is that produced by the predetermined number (N) or more signal paths having signals present thereon, and exclusive-OR means connected to the first comparator means and to said enabling means, said exclusive-OR means being operable to produce said first indication during an enabling signal in response to a second output signal from the first comparator means and to produce said second indication during an enabling signal in response to a first output signal from the first comparator means; said second detecting means includes a second comparator means having one input connected to said common juncture and another input connected to a second point of reference potential, said second comparator means being operable to produce said first indication when the voltage at the common juncture is that produced by less than the predetermined number plus one (N+1) signal paths having signals present thereon, and to produce said second indication when the voltage at the common juncture is that produced by the predetermined number plus one (N+1) or more signal paths having signals present thereon.

Claim 7

Apparatus in accordance with claim 4 including first transistor means coupled to said common juncture, said first transistor means being biased to a low conduction condition when the voltage at the common juncture is that produced by less than the predetermined number (N) of signal paths having signals present thereon, being biased in a first high conduction condition when the voltage at the common juncture is that produced by the predetermined number (N) of signal paths having signals present thereon, and being biased in a second high conduction condition when the voltage at the common juncture is that produced by the predetermined number plus one (N+1) or more signal paths having signals present thereon; exclusive-OR means connected to the first transistor means and to said enabling means, said exclusive-OR means being operable to produce said first indication during an enabling signal when said first transistor means is in the first or second high conduction condition and to produce said second indication during an enabling signal when said first transistor means is in the low conduction condition; second transistor means coupled to said first transistor means, said second transistor means being biased to a low conduction condition when said first transistor means is in the low conduction condition or in the first high conduction condition, and being biased to a high conduction condition when said first transistor means is in the second high conduction condition; and third transistor means coupled to the second transistor means and to said output means, said third transistor means being biased to a low conduction condition when said second transistor means is in the low conduction condition thereby producing said first indication to said output means, and being biased to a high conduction condition when said second transistor means is in the high conduction condition thereby producing said second indication to said output means.

Claim 8

Apparatus in accordance with claim 6 wherein said first transistor means includes a first transistor having its base connected to said common juncture, its emitter connected through a resistance to a first source of voltage, and its collector connected through a resistance to a second source of voltage and to said enabling means; and a resistance connected between said first source of voltage and said common juncture; the conducting condition of the first transistor being determined by the voltage produced at the common juncture by the number of signal paths having signals present thereon; said second transistor means includes a second transistor having its emitter connected to the collector of the first transistor, its base connected to a source of voltage, and its collector connected through a resistance to a source of voltage; and said third transistor means includes a third transistor having its base connected to the collector of the second transistor, its collector connected to a point of reference potential, and its emitter connected through a resistance to a voltage source and also to said output means.