US3851307A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two (and only two) out of six check circuit
Assignee: AG Communication Systems Corp
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Filing: 1973-06-25
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Granted: 1974-11-26
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Expires: 1993-06-25
Abstract
Abstract A five stage logic circuit including logic And and Nand gates and wherein each of the stages receives at least one out of six input lines. The output of each And/Nand stage is dependent on the input signal to the stage. If there is an input signal present on two and only two of the six inputs, an output level is indicated at the output of the last stage.
Inventors
- 👤 J Rivas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
174 words
A five stage logic circuit for determining the presence of an input signal on two and only two of six input lines, said logic circuit comprising: a first stage logic circuit having inputs coupled respectively to two of said six lines; a second stage logic circuit having inputs coupled respectively to the output of said first stage logic circuit and to a third of said input lines; a third stage logic circuit having inputs coupled respectively to the output of said second stage logic circuit and to a fourth of said input lines; a fourth stage logic circuit having inputs coupled respectively to the output of said third stage logic circuit and to a fifth of said input lines; a fifth stage logic circuit having inputs coupled respectively to the output of said fourth stage logic circuit and to a sixth of said input lines; and said first through fifth logic circuits including means responsive to the presence of two and only two input signals on said six input lines to provide an output.
Claim 2
Dependent Claim
174 words
A five stage logic circuit for determining the presence of an input signal on two and only two of six input lines, said logic circuit comprising: a first stage logic circuit having inputs coupled respectively to two of said six lines; a second stage logic circuit having inputs coupled respectively to the output of said first stage logic circuit and to a third of said input lines; a third stage logic circuit having inputs coupled respectively to the output of said second stage logic circuit and to a fourth of said input lines; a fourth stage logic circuit having inputs coupled respectively to the output of said third stage logic circuit and to a fifth of said input lines; a fifth stage logic circuit having inputs coupled respectively to the output of said fourth stage logic circuit and to a sixth of said input lines; and said first through fifth logic circuits including means responsive to the presence of two and only two input signals on said six input lines to provide an output.
Claim 3
Dependent Claim
25 words
A five stage logic circuit according to claim 1, including inverter means for respectively inverting said input signAl level on each of said input lines.
Claim 4
Dependent Claim
32 words
A five stage logic circuit according to claim 2, including means for respectively coupling the non-inverted and inverted input signals of two of said input lines to said first stage logic circuit.
Claim 5
Dependent Claim
35 words
A five stage logic circuit according to claim 3, including means for coupling the non-inverted and inverted signal levels on said remaining four input lines respectively to said second, third, fourth and fifth logic stages.
Claim 6
Dependent Claim
43 words
A five stage logic circuit according to claim 1, including a final logic gate responsive to the output of said fifth logic stage to provide an output signal upon the detection of two and only two input signals on said six input lines.
Claim 7
Dependent Claim
19 words
A five stage logic circuit according to claim 1, wherein the first through fifth logic stages includes And gates.
Claim 8
Dependent Claim
19 words
A five stage logic circuit according to claim 6, wherein said first through fifth logic stages includes Nand gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-25 | 1978-05-27 | 1978-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-25 | 1982-05-27 | 1982-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-25 | 1986-05-27 | 1986-11-26 | $7700.00 | Window Closed / Lapsed |