US3633180A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error-detecting circuit for graphic-programming matrix
Assignee: Licentia Patent Verwaltungs GmbH
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Filing: 1969-11-17
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Granted: 1972-01-04
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Expires: 1989-11-17
Abstract
Abstract A circuit for indicating the erroneous simultaneous contacting of two adjacent intersections of a matrix composed of two sets of conductive strips disposed adjacent and at right angles to one another, which circuit includes a plurality of AND elements each connected to two adjacent, parallel conductive strips for producing an output signal when both strips have been simultaneously contacted, and a further logic element connected to the outputs of all of the AND elements for producing an error indication whenever an output signal is produced by one of the AND elements.
Inventors
- 👤 Wolfgang Pabst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:33
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/08; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
190 words
Error-detecting means for use with a graphic-programming matrix composed of two sets of parallel, mutually isolated conductive strips disposed adjacent one another, with one set of strips extending transversely to the other set and being arranged so that a pressure applied at any point of the matrix will bring one strip of one set into contact with one strip of the other set, and a voltage supply connected to both sets of strips for applying reading currents thereto, said error-detecting means providing an error indication whenever two adjacent strips of one set are contacted simultaneously by at least one strip of the other set and comprising, in combination: a plurality of logic element means each connected to one respective strip of one said set for producing an output whenever the strip of said one set to which it is connected is being contacted by any strip of the other set; and logic circuit means connected to the outputs of said logic element means for producing an error indication signal whenever an output is being produced simultaneously by two of said plurality of logic element means which are adjacent one another.
Claim 2
Dependent Claim
190 words
Error-detecting means for use with a graphic-programming matrix composed of two sets of parallel, mutually isolated conductive strips disposed adjacent one another, with one set of strips extending transversely to the other set and being arranged so that a pressure applied at any point of the matrix will bring one strip of one set into contact with one strip of the other set, and a voltage supply connected to both sets of strips for applying reading currents thereto, said error-detecting means providing an error indication whenever two adjacent strips of one set are contacted simultaneously by at least one strip of the other set and comprising, in combination: a plurality of logic element means each connected to one respective strip of one said set for producing an output whenever the strip of said one set to which it is connected is being contacted by any strip of the other set; and logic circuit means connected to the outputs of said logic element means for producing an error indication signal whenever an output is being produced simultaneously by two of said plurality of logic element means which are adjacent one another.
Claim 3
Dependent Claim
65 words
An arrangement as defined in claim 1 wherein said logic circuit means comprises: a plurality of AND gates each having two inputs connected to the outputs of a respective adjacent pair of said logic element means; and an OR gate having a plurality of inputs connected to the outputs of all of said AND gates and an output at which appears an error indication signal.
Claim 4
Dependent Claim
97 words
An arrangement as defined in claim 2 wherein said voltage supply includes means to apply a positive polarity voltage to one said set of strips and a negative polarity voltage of the same amplitude to the other of said set of strips and vice versa so that when a strip of one set contacts a strip of the other set, a zero amplitude voltage is present on both said strips, and wherein each said logic element means includes means for producing an output whenever a zero voltage is present on its respective strip of saiD one set.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-03 | 1975-07-05 | 1976-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-03 | 1979-07-05 | 1980-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-03 | 1983-07-05 | 1984-01-04 | $7700.00 | Window Closed / Lapsed |