US3582892A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense, store and interlock matrix circuit for a switching device
Assignee: International Business Machines Corp
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Filing: 1968-10-29
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Granted: 1971-06-01
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Expires: 1988-10-29
Abstract
Abstract A circuit is provided which operates in combination with a matrix switch. The circuit senses a switch closure, stores a pair of output signals representative of the closed switch, cancels the effect of a second switch closure or multiple switch closure during the storage period and resets at the end of the storage period. The circuit includes a plurality of transistor latching means connected to the matrix switch, pairs of which are set by switch closures. Clamping diodes are provided to balance the latching means to prevent spontaneous setting. A switch interlock transistor is included to prevent any subsequent switch closures prior to reset from producing an output signal. A transistor arrangement is also included to cancel the output signals when two or more switches are erroneously closed at the same time. At the end of a selected time period, reset transistors are actuated to reset the circuit to its original state.
Inventors
- 👤 Hans Y Juliusburger
- 👤 George R Stilwell Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:16
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/02; G; G06; G06K; G06K15/00; G06K15/02; G06K15/10
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
219 words
A switching circuit comprising a first plurality of N conductors, a second plurality of M conductors, a first plurality of N latching means, each one adapted to be switched from a reset to a set condition and each one connected to a separate one of said N conductors of Said switching device, a second plurality of M latching means, each one adapted to be switched from a reset to a set condition and each one connected to a separate one of said M conductors, a voltage source connected to said first and second plurality of latching means, and a plurality of N X M switching elements, each one of said switching elements connected between a separate combination of one of said N conductors and one of said M conductors, each of said N X M switching elements adapted to be closed to electrically connect a discrete one of said N conductors to a discrete one of said M conductors to produce a current path from said voltage source through said closed switch element and a discrete one of said M latching means to switch said N and M latching means connected to said discrete N and M conductors to said set condition, said latching means in said set condition being representative of the particular switching element which is closed.
Claim 2
Dependent Claim
219 words
A switching circuit comprising a first plurality of N conductors, a second plurality of M conductors, a first plurality of N latching means, each one adapted to be switched from a reset to a set condition and each one connected to a separate one of said N conductors of Said switching device, a second plurality of M latching means, each one adapted to be switched from a reset to a set condition and each one connected to a separate one of said M conductors, a voltage source connected to said first and second plurality of latching means, and a plurality of N X M switching elements, each one of said switching elements connected between a separate combination of one of said N conductors and one of said M conductors, each of said N X M switching elements adapted to be closed to electrically connect a discrete one of said N conductors to a discrete one of said M conductors to produce a current path from said voltage source through said closed switch element and a discrete one of said M latching means to switch said N and M latching means connected to said discrete N and M conductors to said set condition, said latching means in said set condition being representative of the particular switching element which is closed.
Claim 3
Dependent Claim
63 words
A switching circuit according to claim 1 further including N gating means, each one connected to a separate one of said N latching means, said gating means being responsive to the current in said current path produced when an associated one of said switching elements is closed to cause an associated one of said N latching means to switch to the set condition.
Claim 4
Dependent Claim
59 words
A switching circuit according to claim 1 further including means for providing a first current path from said voltage source through said N latching means in said set condition and a second current path from said voltage source through said M latching means in said set condition to maintain said N and M latching means in said set condition.
Claim 5
Dependent Claim
44 words
A switching circuit according to claim 1 further including interlock signal means connected to said first plurality of latching means for producing an interlock signal after a switch element is closed, said interlock signal maintaining said remaining reset latching means in said reset condition.
Claim 6
Dependent Claim
52 words
A switching circuit according to claim 1 further including reset signal means connected to said first and second plurality of latching means for producing a reset signal a predetermined time after a switch element is closed for switching said discrete one of said latching means from said set to said reset condition.
Claim 7
Dependent Claim
56 words
A switching circuit according to claim 1 wherein each of said N and M latching means includes first and second transistors, having emitter, base and collector electrodes, said first transistor not conducting and said second transistor conducting in said reset condition and said first transistor conducting and said second transistor not conducting in said set condition.
Claim 8
Dependent Claim
52 words
A switching circuit according to claim 3 further including means connected to said first and second current paths for producing an output signal when the value of current in said first and second current paths exceeds a predetermined value in response to more than one of said switching elements being closed simultaneously.
Claim 9
Dependent Claim
200 words
A switching circuit according to claim 6 further including N gating transistors having collector, emitter and base electrodes, a first electrode of each of said N gating transistors connected to one of said first and second transistors of a separate one of said N latching means, a second electrode of each of said N gating transistors connected to a separate one of said N conductors, a third electrode of each of said N gating transistors connected to said voltage source, a first electrode of each of said first transistors of said M gating means connected to a separate one of said M conductors, a current path being formed when one of said switch elements is closed from said voltage source on said discrete N conductor through said closed switch and on said discrete M conductor to said first transistor in said discrete one of said M latching means connected to said discrete M conductor to switch said N and M latching means connected to said discrete conductors to the set condition wherein said first transistors in said set N and M latching means are conducting and said second transistors in said set N and M latching means are not conducting.
Claim 10
Dependent Claim
59 words
A switching circuit according to claim 8 further including means for providing a first current path from said voltage source through said N latching means in said set condition and a second current path from said voltage source through said M latching means in said set condition to maintain said N and M latching means in said set condition.
Claim 11
Dependent Claim
44 words
A switching circuit according to claim 8 further including interlock signal means connected to said first plurality of latching means for producing an interlock signal after a switch element is closed, said interlock signal maintaining said remaining reset latching means in said reset condition.
Claim 12
Dependent Claim
52 words
A switching circuit according to claim 8 further including reset signal means connected to said first and second plurality of latching means for producing a reset signal a predetermined time after a switch element is closed for switching said discrete one of said latching means from said set to said reset condition.
Claim 13
Dependent Claim
106 words
A switching circuit according to claim 8 wherein the collector electrode of each of said N gating transistors is connected to the emitter electrode of said second transistor in a separate one of said N latching means, the collector electrode of each of said N gating transistors connected to said voltage source, and the base electrode of each of said gating transistors connected to a separate one of said N conductors, the closing of a switching element causing the associated gating transistor connected thereto to be biased off thereby causing the second transistor of said latching means connected to said gating transistor to be biased off.
Claim 14
Dependent Claim
106 words
A switching circuit according to claim 8 wherein the collector electrode of each of said N gating transistors is connected to the collector electrode of said first transistor in a separate one of said N latching means, the base electrode of each of said N gating transistors connected to said voltage source, and the emitter electrode of each of said gating transistors connected to a separate one of said N conductors, the closing of a switching element causing the associated gating transistor connected thereto to be biased on thereby causing the first transistor of said latching means connected to said gating transistor to be biased on.
Claim 15
Dependent Claim
91 words
A switching circuit according to claim 8 further including a reference level source connected to emitter electrode of the first transistor of each of said N and M latching means for providing a first current path from said voltage source through the first transistor of said one of said N latching means in said set condition to said reference level source, and a second current path from said voltage source through the first transistor of said one of said M latching means in said set condition to said reference level source.
Claim 16
Dependent Claim
58 words
A switching circuit according to claim 14 further including an interlock transistor connected to the collector electrodes of said first and second transistors of said N latching means, and a source of interlock signal connected to said interlock transistor to operate said interlock transistor to prevent further latching mans being set during the duration of said interlock signal.
Claim 17
Dependent Claim
97 words
A switching circuit according to claim 14 further including a first reset transistor connected between the emitter electrodes of each of said first transistors of sand N latching means and said reference level source and a second reset transistor connected between the emitter electrodes of each of said first transistors of said M latching means and said reference level source, and a source of reset signal connected to said first and second reset transistors for operating said reset transisTors to cause said set ones of said N and M latching means to switch to the reset condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |