Method of manufacturing a field-effect transistor

Claim 1

A METHOD OF MANUFACTURING A FIELD-EFFECT TRANSISTOR COMPRISING BASE, SOURCE AND DRAIN REGIONS, A GATE ELECTRODE AND A GATE INSULATING LAYER, WHICH COMPRISES THE STEPS : A. FORMING A THICK INSULATING LAYER, HAVING A THICKNESS WHICH IS GREATER THAN THE DIFFUSION LENGTH OF AN IMPURITY FORMING A BASE REGION IN A FOLLOWING PROCESS STEP, ON A SURFACE OF A SEMICONDUCTOR SUBSTRATE INCLUDING AN IMPURITY OF A FIRST CONDUCTIVITY TYPE, B. REMOVING A PORTION OF SAID THICK INSULATING LAYER FROM THE SURFACE OF SAID SEMICONDUCTOR SUBSTRATE TO LEAVE AT LEAST ONE ISLAND-LIKE PORTION OF SAID THICK INSULATING LAYER ON SAID SURFACE, C. DIFFUSING FIRST AND SECOND IMPURITIES SUCCESSIVELY INTO SAID SURFACE OF SAID SUBSTRATE WHILE USING SAID ISLAND-LIKE PORTION AS A DIFFUSION MASK TO FORM BASE AND SOURCE REGIONS, RESPECTIVELY, IN SAID SUBSTRATE BY DIFFUSING SAID FIRST IMPURITY TO A GREATER DEPTH THAN SAID SECOND IMPURITY, SAID FIRST IMPURITY BEING OF A SECOND CONDUCTIVITY TYPE OPPOSITE TO SAID FIRST CONDUCTIVITY TYPE AND SAID SECOND IMPURITY BEING OF SAID FIRST CONDUCTIVITY TYPE WHEREBY SAID SUBSTRATE BECOMES A DRAIN REGION, D. ETCHING AWAY A PORTION OF SAID ISLAND-LIKE INSULATING LAYER TO LEAVE A PORTION O SAID ISLND-LIKE INSULATING LAYER ON THE SURFACE OF SAID DRAIN REGION AND TO EXPOSE THE SURFACE OF SAID BASE REGION, E. FORMING AN INSULATING LAYER THINNER THAN THE THICKNESS OF SAID REMAINING-ISLAND LIKE INSULATING LAYER ON THE EXPOSED SURFACE OF SAID BASE, SOURCE AND DRAIN REGIONS TO FORM A GATE INSULATING LAYER CONSISTING OF SAID ISLAND-LIKE INSULATING LAYER AND SAID THIN INSULATING LAYER, AND F. THEN FORMING A GATE ELECTRODE ON SAID GATE INSULATING LAYER.

Claim 2

A METHOD OF MANUFACTURING A FIELD-EFFECT TRANSISTOR COMPRISING BASE, SOURCE AND DRAIN REGIONS, A GATE ELECTRODE AND A GATE INSULATING LAYER, WHICH COMPRISES THE STEPS : A. FORMING A THICK INSULATING LAYER, HAVING A THICKNESS WHICH IS GREATER THAN THE DIFFUSION LENGTH OF AN IMPURITY FORMING A BASE REGION IN A FOLLOWING PROCESS STEP, ON A SURFACE OF A SEMICONDUCTOR SUBSTRATE INCLUDING AN IMPURITY OF A FIRST CONDUCTIVITY TYPE, B. REMOVING A PORTION OF SAID THICK INSULATING LAYER FROM THE SURFACE OF SAID SEMICONDUCTOR SUBSTRATE TO LEAVE AT LEAST ONE ISLAND-LIKE PORTION OF SAID THICK INSULATING LAYER ON SAID SURFACE, C. DIFFUSING FIRST AND SECOND IMPURITIES SUCCESSIVELY INTO SAID SURFACE OF SAID SUBSTRATE WHILE USING SAID ISLAND-LIKE PORTION AS A DIFFUSION MASK TO FORM BASE AND SOURCE REGIONS, RESPECTIVELY, IN SAID SUBSTRATE BY DIFFUSING SAID FIRST IMPURITY TO A GREATER DEPTH THAN SAID SECOND IMPURITY, SAID FIRST IMPURITY BEING OF A SECOND CONDUCTIVITY TYPE OPPOSITE TO SAID FIRST CONDUCTIVITY TYPE AND SAID SECOND IMPURITY BEING OF SAID FIRST CONDUCTIVITY TYPE WHEREBY SAID SUBSTRATE BECOMES A DRAIN REGION, D. ETCHING AWAY A PORTION OF SAID ISLAND-LIKE INSULATING LAYER TO LEAVE A PORTION O SAID ISLND-LIKE INSULATING LAYER ON THE SURFACE OF SAID DRAIN REGION AND TO EXPOSE THE SURFACE OF SAID BASE REGION, E. FORMING AN INSULATING LAYER THINNER THAN THE THICKNESS OF SAID REMAINING-ISLAND LIKE INSULATING LAYER ON THE EXPOSED SURFACE OF SAID BASE, SOURCE AND DRAIN REGIONS TO FORM A GATE INSULATING LAYER CONSISTING OF SAID ISLAND-LIKE INSULATING LAYER AND SAID THIN INSULATING LAYER, AND F. THEN FORMING A GATE ELECTRODE ON SAID GATE INSULATING LAYER.