US3906155A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for generating a control signal for the field output stage in a television receiver
Assignee: US Philips Corp
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Filing: 1973-06-01
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Granted: 1975-09-16
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Expires: 1993-06-01
Abstract
Abstract A circuit arrangement for generating a control signal for the field output stage in a television receiver provided with a frequency divider circuit with which the double line frequency is divided either by a number which is equal to the number of lines per image or by a number which deviates from this number. The choice between the two divisors is made by a storage element dependent on the on-phase state or the off-phase state of the received field synchronizing pulses and the divider pulses. Resetting of the frequency divider circuit is therefore realised by the store and not by the received pulses, which results in less sensitivity to interference. Since there are two states, a small brightly lit image no longer occurs. In the case of the nominal divisor, the divider pulse is extended. When receiving non-standard signals (for example, from video recorders) direct synchronisation is used with the divisor being larger than the nominal divisor.
Inventors
- 👤 Straaten Jan Van
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:44
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
214 words
A circuit arrangement for generating a control signal for the field output stage in a television receiver, said circuit comprising means for the reception of line and field synchronising pulses in which a number of fields constitutes an image raster, a generator means coupled to said reception means for generating a signal of the line frequency or an integer multiple thereof, a frequency divider circuit coupled to said generator means and having a first state wherein the divisor equals the number of lines per image and a second state wherein the divisor deviates from said number, a comparator stage means for continuously comparing said received field synchronization pulses with an output signal from said frequency divider having a first input means coupled to said reception means for receiving said field synchronization pulses, a second input coupled to said divider, and an output means for supplying a signal which is dependent on the phase difference between the compared pulses, a memory element means coupled to said output means for bringing and maintaining the frequency divider circuit in its first state when the compared pulses at least partly coincide and brings it to the second state when the compared pulses have not coincided for a given period, and a gate coupled between said memory and divider.
Claim 2
Dependent Claim
214 words
A circuit arrangement for generating a control signal for the field output stage in a television receiver, said circuit comprising means for the reception of line and field synchronising pulses in which a number of fields constitutes an image raster, a generator means coupled to said reception means for generating a signal of the line frequency or an integer multiple thereof, a frequency divider circuit coupled to said generator means and having a first state wherein the divisor equals the number of lines per image and a second state wherein the divisor deviates from said number, a comparator stage means for continuously comparing said received field synchronization pulses with an output signal from said frequency divider having a first input means coupled to said reception means for receiving said field synchronization pulses, a second input coupled to said divider, and an output means for supplying a signal which is dependent on the phase difference between the compared pulses, a memory element means coupled to said output means for bringing and maintaining the frequency divider circuit in its first state when the compared pulses at least partly coincide and brings it to the second state when the compared pulses have not coincided for a given period, and a gate coupled between said memory and divider.
Claim 3
Dependent Claim
55 words
A circuit arrangement as claimed in claim 1, further comprising an adjusting gate means coupled to said divider and said memory element for adjusting the frequency divider circuit every time at the commencement of each raster, said adjusting gate having an input means for adjusting the frequency divider circuit by means of the memory element.
Claim 4
Dependent Claim
46 words
A circuit arrangement as claimed in claim 1, wherein the memory element comprises a bistable element means for receiving reset pulses when the compared pulses coincide at least partly and and for receiving set pulses when the compared pulses have not coincided for a given period.
Claim 5
Dependent Claim
65 words
A circuit arrangement as claimed in claim 3, wherein the divisor in the divider in the second state is larger than that in the first state, and further comprising means coupled to the bistable element in the memory element for preventing reset pulses from being received by said bistable element while the frequency divider circuit is being adjusted by means of received field synchronizing pulses.
Claim 6
Dependent Claim
99 words
A circuit arrangement as claimed in claim 1, further comprising a pulse shaper having an input coupled to said memory and an output means for applYing a pulsatory output signal to the comparator stage, the memory element bringing the pulse shaper to a first state when it brings the frequency divider circuit to its first state, the duration of the output pulse from the pulse shaper in its first state being longer than in a second state to which the pulse shaper is brought by the memory element when it brings the frequency divider circuit to its second state.
Claim 7
Dependent Claim
102 words
A circuit arrangement as claimed in claim 5, wherein the frequency divider circuit comprises a plurality of serially coupled bistable elements and the pulse shaper includes a keyed gate having a first state in which it receives the output signal from a divider bistable element and a second state in which it receives the output signal from another divider bistable element, the period of the former output signal being longer than the period of the latter, the output signal from the keyed gate being the first half period of the relevant output signal after the instant of resetting the frequency divider circuit.
Claim 8
Dependent Claim
81 words
A circuit arrangement as claimed in claim 1 wherein the frequency divider circuit comprises a plurality of serially coupled bistable elements, and further comprising an adjusting gate having a plurality of inputs, the outputs of a plurality of the divider bistable elements being coupled to inputs of said adjusting gate for adjusting the frequency divider circuit at the commencement of each raster, and a controllable switch coupled between one of said plurality of inputs and one of said plurality of outputs.
Claim 9
Dependent Claim
22 words
A circuit arrangement as claimed in claim 7, wherein the difference between the two divisors is a combination of powers of 2.
Claim 10
Dependent Claim
18 words
A circuit arrangement as claimed in claim 7 wherein said memory element is coupled to said controllable switch.
Claim 11
Independent Claim
87 words
A method comprising generating a television line frequency signal or an integral multiple thereof from a received line synchronization signal, said method comprising obtaining a field synchronization signal by frequency dividing said generated signal by a first divisor, continuously detecting lack of synchronization between said obtained field frequency signal and a received field frequency signal, changing said divisor in said dividing step to a second divisor upon detecting said lack of synchronization, and changing said divisor back to said first divisor upon detecting synchronization between said signals.
Claim 12
Independent Claim
87 words
A method comprising generating a television line frequency signal or an integral multiple thereof from a received line synchronization signal, said method comprising obtaining a field synchronization signal by frequency dividing said generated signal by a first divisor, continuously detecting lack of synchronization between said obtained field frequency signal and a received field frequency signal, changing said divisor in said dividing step to a second divisor upon detecting said lack of synchronization, and changing said divisor back to said first divisor upon detecting synchronization between said signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |