US3567857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse inhibit circuit
Assignee: HP Inc
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Filing: 1968-03-15
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Granted: 1971-03-02
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Expires: 1988-03-15
Abstract
Abstract The picture signal is removed from an amplified composite video input signal by a sync stripper. Vertical sync pulses extracted from the remaining composite synchronizing signal periodically enable a gate to pass portions of a timing signal from an oscillator operating at twice the horizontal line rate. The gated portions of this timing signal periodically trigger a vertical deflection circuit to initiate retrace of the vertical field scans of an electron beam of a cathode ray tube. A binary scaler halves the repetition rate of the timing signal from the oscillator. The resultant signal periodically triggers a horizontal deflection circuit to initiate retrace of the horizontal line scans of the electron beam of the cathode ray tube. An automatic phase control circuit locks the oscillator in phase with the composite synchronizing signal and stabilizes the rate of the timing signal at twice the horizontal line rate. In response to the signals from the oscillator and the binary scaler a control gate passes the horizontal timing portions of the composite synchronizing signal and inhibits passage of double frequency portions in the vertical synchronizing interval of the composite synchronizing signal. The horizontal timing portions are regenerated by a blocking oscillator and supplied to the automatic phase control circuit for phase and frequency comparison with a ramp signal generated in phase with and at the rate of the signal from the binary scaler. When the compared signals are not within the pull-in range of the automatic phase control circuit another control circuit prevents the inhibit cycle of the control gate.
Inventors
- 👤 Robert E Lynn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:37
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H04N5/126
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
113 words
A circuit for extracting a first train of signals having a first repetition rate from a second train of signals having a second repetition rate equal to an even integral multiple n of the first repetition rate, said circuit comprising: a control circuit for receiving the second train of signals: and means for providing a third train of signal having the first repetition rate, said means being connected to said control circuit for supplying the third train of signals to the control circuit in coincidence with every nth signal of the second train; said control circuit being responsive to the second and third trains of signals for providing the first train of signals.
Claim 2
Dependent Claim
113 words
A circuit for extracting a first train of signals having a first repetition rate from a second train of signals having a second repetition rate equal to an even integral multiple n of the first repetition rate, said circuit comprising: a control circuit for receiving the second train of signals: and means for providing a third train of signal having the first repetition rate, said means being connected to said control circuit for supplying the third train of signals to the control circuit in coincidence with every nth signal of the second train; said control circuit being responsive to the second and third trains of signals for providing the first train of signals.
Claim 3
Dependent Claim
63 words
A circuit as in claim 1 wherein said means comprises: an oscillator for producing a fourth train of signals having the second repetition rate; and first control means connected to said oscillator for producing the third train of signals from the fourth train of signals, said first control means being connected to said control circuit for supplying the third train of signals thereto.
Claim 4
Dependent Claim
56 words
A circuit as in claim 2 wherein said first control means comprises: a divider connected to said oscillator for dividing the repetition rate of the fourth train of signals by n to produce the third train of signals; and means for connecting said divider to said control circuit to supply the third train of signals thereto.
Claim 5
Dependent Claim
83 words
A circuit as in claim 2 wherein said first control means comprises: a divider connected to said oscillator for dividing the repetition rate of the fourth train of signals by n to produce a fifth train of signals; and means connected to said oscillator and to said divider and responsive to the fourth and fifth trains of signals therefrom for producing the third train of signals; said last-mentioned means being connected to said control circuit for supplying the third train of signals thereto.
Claim 6
Dependent Claim
84 words
A circuit as in claim 2 including: a feedback circuit connected to said oscillator for locking the oscillator in phase with the second train of signals and for stabilizing the repetition rate of the fourth train of signals at the second repetition rate; and second control means connected between said feedback circuit and said control circuit, said second control means being responsive to operation of the feedback circuit beyond its pull-in range for causing the control circuit to provide the second train of signals.
Claim 7
Dependent Claim
78 words
A circuit as in claim 5 wherein: said integral multiple n equals two so that the second repetition rate; and said control circuit comprises a gate, said gate being disabled by the signals of the third train to inhibit passage of every other signal of the second train and being enabled during the intervals between successive signals of the third train to pass the remaining signals of the second train and thereby provide the first train of signals.
Claim 8
Dependent Claim
147 words
A circuit as in claim 6 wherein said feedback circuit includes: a scale of two divider connected to said oscillator for halving the repetition rate of the fourth train of signals to produce signals having the first repetition rate; phase comparison means responsive to a train of the signals from said scale of two divider and to the train of signals passed by said gate for producing a signal related to the phase difference between these trains of signals; and third control means including a low pass filter connecting said phase comparison means to said oscillator, said third control means being responsive to the signal from said phase comparison means for supplying said oscillator with an error signal to lock the oscillator in phase with the second train of signals and to stabilize the repetition rate of the fourth train of signals at the second repetition rate.
Claim 9
Dependent Claim
121 words
A circuit as in claim 7 wherein said second control means includes: AC coupling means connected to said third control means and operable for passing an AC beat portion of the error signal therefrom, said AC beat portion being produced when the phase difference between a train of the signals from said scale of two divider and the train of signals passed by said gate is beyond the pull-in range of said feedback circuit; and means connected between said AC coupling meaNs and said gate and responsive to the AC beat portion of the error signal for supplying the gate with a control signal to prevent its inhibit cycle and thereby cause the gate to pass the second train of signals.
Claim 10
Dependent Claim
37 words
A circuit as in claim 8 wherein said first control means comprises: said scale of two divider; and means for connecting said scale of two divider to said gate to supply the third train of signals thereto.
Claim 11
Dependent Claim
79 words
A circuit as in claim 8 wherein said first control means comprises: said scale of two divider; and another gate connected to said oscillator and to said scale of two divider and responsive to the fourth train of signals from said oscillator and to a train of the signals from said scale of two divider for providing the third train of signals, said other gate being connected to said first-mentioned gate for supplying the third train of signals thereto.
Claim 12
Dependent Claim
141 words
A circuit for inhibiting signals occurring during the time intervals between selected signals having a desired repetition rate in a first train of signals to provide a second train of signals having the desired repetition rate, said circuit comprising: a control circuit for receiving the firs t train of signals: and means for providing a third train of signals having the desired repetition rate and occurring during the time intervals between the selected signals of the first train, said means being connected to said control circuit for supplying the third train of signals to the control circuit during the time intervals between the selected signals of the first train; said control circuit being responsive to the third train of signals for inhibiting signals of the first train that occur during the time intervals between the selected signals of the firs train.
Claim 13
Dependent Claim
141 words
A circuit for inhibiting signals occurring during the time intervals between selected signals having a desired repetition rate in a first train of signals to provide a second train of signals having the desired repetition rate, said circuit comprising: a control circuit for receiving the firs t train of signals: and means for providing a third train of signals having the desired repetition rate and occurring during the time intervals between the selected signals of the first train, said means being connected to said control circuit for supplying the third train of signals to the control circuit during the time intervals between the selected signals of the first train; said control circuit being responsive to the third train of signals for inhibiting signals of the first train that occur during the time intervals between the selected signals of the firs train.
Claim 14
Dependent Claim
68 words
A circuit as in claim 11 wherein said means comprises: an oscillator for producing a fourth train of signals; and control means connected to said oscillator for producing the third train of signals from the fourth train of signals, said control means being connected to said control circuit for supplying the third train of signals thereto during the time intervals between the selected signals of the first train.
Claim 15
Dependent Claim
110 words
A circuit as in claim 12 wherein said control circuit comprises a gate having a first input for receiving the first train of signals, a second input for receiving the third train of signals, and an output, said gate being disabled the the signals of the third train to inhibit passage of signals of the first train that occur during the time intervals between the selected signals of the first train and being enabled during the time intervals between successive signals of the third train to pass the selected signals of the first train and thereby provide the second train of signals having the desired repetition rate at its output.
Claim 16
Dependent Claim
80 words
A circuit as in claim 13 wherein said control means comprises: means connected to said oscillator for deriving a fifth train of signals from the fourth train of signals; and another gate connected to said oscillator and to said last-mentioned means and responsive to said fourth and fifth trains of signals therefrom for providing the third train of signals, said other gate being connected to the second input of said first-mentioned gate for supplying the third train of signals thereto.
Claim 17
Dependent Claim
148 words
A circuit for extracting a first train of signals having a first repetition rate from a second train of signals having a second repetition rate equal to an integral multiple n of the first repetition rate, said circuit comprising: a control circuit having a first input for receiving the second train of signals, having a second input, and having an output; first means for producing a third train of signals having the second repetition rate; and second means connected to said first means and responsive to the third train of signals therefrom for producing a fourth train of signals having the first repetition rate, said sEcond means being connected to the second input of said control circuit for supplying the fourth train of signals thereto; said control circuit being responsive to the second and fourth trains of signals for providing the first train of signals at its output.
Claim 18
Dependent Claim
148 words
A circuit for extracting a first train of signals having a first repetition rate from a second train of signals having a second repetition rate equal to an integral multiple n of the first repetition rate, said circuit comprising: a control circuit having a first input for receiving the second train of signals, having a second input, and having an output; first means for producing a third train of signals having the second repetition rate; and second means connected to said first means and responsive to the third train of signals therefrom for producing a fourth train of signals having the first repetition rate, said sEcond means being connected to the second input of said control circuit for supplying the fourth train of signals thereto; said control circuit being responsive to the second and fourth trains of signals for providing the first train of signals at its output.
Claim 19
Dependent Claim
105 words
A circuit as in claim 15 wherein: said first means comprises an oscillator for producing the third train of signals, and a divider connected to said oscillator for dividing the repetition rate of the third train of signals by n to produce a fifth train of signals having the first repetition rate; and said second means is connected to said oscillator and to said divider and is responsive to the third nand fifth trains of signals therefrom for producing the fourth train of signals, said seconds means being connected to the second input of said control circuit for supplying the fourth train of signals thereto.
Claim 20
Dependent Claim
88 words
A circuit as in claim 16 wherein: said integral multiple n equals two so that the second repetition rate equals twice the first repetition rate; and said control circuit comprises a first gate, said gate being disabled by the signals of the fourth train to inhibit passage of every other signal of the second train and being enabled during the intervals between successive signals of the fourth train to pass the remaining signals of the second train and thereby provide the first train of signals at its output.
Claim 21
Dependent Claim
71 words
A circuit as in claim 17 wherein said second means comprises a second gate connected to said oscillator and to said divider and responsive to the third train of signals from said oscillator and to the fifth train of signals from said divider for providing the fourth train of signals, said second gate being connected to the second input of said first gate for supplying the fourth train of signals thereto.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |