Vertical synchronizing circuitry

Claim 2

In a television receiver having a signal receiver, a synchronizing pulse Separator connected thereto, and vertical and horizontal circuits for generating scanning signals in synchronism with a received television signal, improved vertical synchronizing circuitry comprising: pulse providing means connected to said synchronizing pulse separator for providing pulses synchronized with said received television signal; counting means connected to said pulse providing means for receiving and counting the pulses therefrom for a predetermined number of counts corresponding to one vertical scanning field; first detecting means connected to said synchronizing pulse separator and to said counting means for synchronizing said counting means with said received television signal when an out-of-synchronization condition is detected; output means connected to said counting means for providing an output pulse each time said counting means counts said predetermined number of counts; and second detecting means connected to said counting means and to said synchronizing pulse separator for detecting the presence of an interlaced relationship between the vertical and horizontal synchronizing pulses and for modifying the operation of said counting means in the absence of a detected interlaced relationship.

Claim 3

Vertical synchronizing circuitry as defined in claim 1 wherein said second detecting means detects the presence or absence of serrations of the vertical synchronizing pulse or of equalizing pulses.

Claim 4

Vertical synchronizing circuitry as defined in claim 1 wherein said counting means includes a counter including reset means and further includes gating means connected to said counter for providing a reset signal to said reset means to reset said counter when the state of said counter indicates that said predetermined number of counts have been counted.

Claim 5

Vertical synchronizing circuitry as defined in claim 3 wherein said pulse providing means is synchronized to the horizontal synchronizing pulses and generates pulses at a rate twice the rate of horizontal synchronizing pulses and wherein said reset means resets said counter every 525 counts.

Claim 6

Vertical synchronizing circuitry as defined in claim 2 wherein said second detecting means includes a first gating means connected to said counting means for gating output pulses from said synchronizing pulse separator therethrough during a predetermined gating interval, second counting means for counting the number of pulses from said synchronizing pulse separator during said gating interval, second gating means connected to said second counting means for providing a signal indicative of the count attained by said second counting means, and means connecting said second gating means to said first detecting means for causing said first-named counting means to be reset by each vertical synchronizing pulse of said received television signal.

Claim 7

Vertical synchronizing circuitry as defined in claim 5 wherein said means connecting said second means to said first detecting means includes integrating means connected to said second gating means, said second gating means discharging said integrating means when said second counting means attains a predetermined count, and switching means connected to said integrating means for switching from a first state to a second state when said integrating means is not discharged for a predetermined number of vertical scanning fields.

Claim 8

Vertical synchronizing circuitry as defined in claim 1 including pulse forming means connected for receiving vertical synchronizing pulses from said synchronizing pulse separator and for providing pulses of controlled duration and amplitude in response thereto to said first detecting means.

Claim 9

Vertical synchronizing circuitry as defined in claim 1 wherein said output means includes pulse forming means for providing output pulses of controlled duration and amplitude.

Claim 10

Vertical synchronizing circuitry as defined in claim 1 wherein said counting means includes a counter, first gating means connected to said counter for providing a signal during predetermined range of counts of said counter, means connected between said first gating means and said counter for developing a reset signal for resetting said counter in response to the signal from said first gating means, and said first detecting means includes means connected to said first gating means and to said synchronizing pulse separator for providing an output signal after a predetermined number of vertical scanning fields during which the signal from said first gating means is not coincident with vertical synchronizing pulses from said synchronizing pulse separator, and second gating means connected to said means for providing an output signal after a predetermined number of vertical scanning fields, said synchronizing pulse separator, and to a reset input of said counting means for coupling a vertical synchronizing pulse to said reset input in response to an output signal from said means for providing an output signal after a predetermined number of vertical scanning fields.

Claim 11

Vertical synchronizing circuitry as defined in claim 9 wherein said means for providing an output signal after a predetermined number of vertical scanning fields includes integrating means and means for discharging said integrating means connected to said first gating means, to said synchronizing pulse separator, and to said integrating means for discharging said integrating means when the signal from said first gating means is coincident with a vertical synchronizing pulse.

Claim 12

In a television receiver having a signal receiver for processing a received television signal to provide a composite video signal, an image display device connected to said signal receiver for displaying an image derived from said composite video signal, a synchronizing pulse separator means connected to said signal receiver for separating synchronizing pulses from said composite video signal, and scanning signal generating means connected to said synchronizing pulse separator means for providing scanning signals to said image display device, improved vertical synchronizing circuitry comprising: pulse providing means connected to said synchronizing pulse separator means for providing pulses synchronized with the horizontal synchronizing pulses of said composite video signal; counting means connected to said pulse providing means for counting the pulses therefrom for a predetermined number of counts corresponding to a vertical scanning field; output means connected to said counting means for providing an output pulse each time said counting means counts said predetermined number of counts; detecting means connected to said synchronizing pulse separator means and to said counting means for detecting an out-of-synchronization condition, said detecting means including first gating means connected to said counting means for providing a signal during a predetermined range of counts of said counting means, integrating means, second gating means connected to said first gating means, to said synchronizing pulse separator means and to said integrating means for discharging said integrating means when the signal from said first gating means is coincident with a vertical synchronizing pulse, and third gating means connected to said integrating means, said synchronizing pulse separator means, and to a reset input of said counting means for providing a reset signal to said counting means when said integrating means is not discharged for a predetermined number of vertical scanning fields.

Claim 13

In a television receiver having a signal receiver for processing a received television signal to provide a composite video signal, an image display device connected to said signal receiver for displaying an image derived from said composite video signal, a synchronizing pulse separator means connected to said signal receiver for separating synchronizing pulses from said composite video signal, and scanning signal generating means connected to said synchronizing pulse separator means for providing scanning signals to said image display device, improved vertical synchronizing circuitry comprising: pulse providing means connected to said synchronizing pulse separator means for providing pulses synchronized with the horizontal synchronizing pulses of said composite video signal; counting means connected to said pulse providing means for counting the pulses therefrom for a predetermined number of counts corresponding to a vertical scanning field; output means connected to said counting means for providing an output pulse each time said counting means counts said predetermined number of counts; detecting means connected to said synchronizing pulse separator means and to said counting means for detecting an out-of-synchronization condition, said detecting means including first gating means connected to said counting means for providing a signal during a predetermined range of counts of said counting means, integrating means, second gating means connected to said first gating means, to said synchronizing pulse separator means and to said integrating means for discharging said integrating means when the signal from said first gating means is coincident with a vertical synchronizing pulse, and third gating means connected to said integrating means, said synchronizing pulse separator means, and to a reset input of said counting means for providing a reset signal to said counting means when said integrating means is not discharged for a predetermined number of vertical scanning fields.

Claim 14

Vertical synchronizing circuitry as defined in claim 11 wherein said synchronizing pulse separator means includes pulse forming means connected for providing pulses of controlled amplitude and duration in response to the vertical synchronizing pulses contained in said composite video signal to said detecting means.

Claim 15

Vertical synchronizing circuitry as defined in claim 12 wherein said pulse forming means includes a monostable multivibrator connected for receiving the vertical synChronizing pulses and for providing the pulses of controlled amplitude and duration.

Claim 16

Vertical synchronizing circuitry as defined in claim 11 wherein said integrating means includes a resistor and capacitor charging circuit, said capacitor being periodically discharged when the signal from said first gating means is coincident with a vertical synchronizing pulse.

Claim 17

Vertical synchronizing circuitry as defined in claim 11 wherein said pulse providing means provides pulses at twice the horizontal line scanning rate and said counting means includes reset means for resetting said counting means every 525 counts.

Claim 18

Vertical synchronizing circuitry as defined in claim 11 wherein said output means includes a monostable multivibrator for providing an output pulse of predetermined amplitude and duration each time said counting means provides a pulse thereto.

Claim 19

In a television receiver having a synchronizing pulse separator for separating synchronizing pulses from a composite video signal, vertical synchronizing circuitry comprising: pulse providing means for providing pulses at a predetermined rate; counting means connected to said pulse providing means for counting the pulses therefrom for a predetermined number of counts corresponding to one vertical scanning field; first detecting means connected to said synchronizing pulse separator and to said counting means for synchronizing said counting means with said synchronizing pulses when an out-of-synchronization condition is detected; and second detecting means connected to said counting means and to said synchronizing pulse separator for detecting the absence of an interlaced relationship between the vertical and horizontal synchronizing pulses and for modifying the operation of said counting means in the absence of an interlaced relationship.

Claim 20

In a television receiver having a synchronizing pulse separator for separating synchronizing pulses from a composite video signal, vertical synchronizing circuitry comprising: pulse providing means for providing pulses at a predetermined rate; counting means connected to said pulse providing means for counting the pulses therefrom for a predetermined number of counts corresponding to one vertical scanning field; first detecting means connected to said synchronizing pulse separator and to said counting means for synchronizing said counting means with said synchronizing pulses when an out-of-synchronization condition is detected; and second detecting means connected to said counting means and to said synchronizing pulse separator for detecting the absence of an interlaced relationship between the vertical and horizontal synchronizing pulses and for modifying the operation of said counting means in the absence of an interlaced relationship.

Claim 21

Vertical synchronizing circuitry as defined in claim 17 wherein said counting means includes a counter and means for resetting said counter at a predetermined count.

Claim 22

Vertical synchronizing circuitry as defined in claim 17 including means connected to said second detecting means and to said synchronizing pulse separator and further connected to said counting means for coupling vertical synchronizing pulses to said counter means when said second detecting means detects the absence of an interlaced relationship.

Claim 23

Vertical synchronizing circuitry as defined in claim 19 wherein said counting means includes a counter and means for resetting said counter at a first predetermined count connected to said second detecting means whereby said second detecting means inhibits said means for resetting said counter from resetting said counter at said first predetermined count and causes said counter to be reset at a second predetermined count.

Claim 24

Vertical synchronizing circuitry as defined in claim 17 wherein said second detecting means detects the absence of serrations of the vertical synchronizing pulses or of equalizing pulses.

Claim 25

Vertical synchronizing circuitry as defined in claim 21 wherein said second detecting means includes gating means connected to said counting means and said synchronizing pulse separator for coupling said synchronizing pulses therethrough during a predetermined range of counts of said counting means, second counting means connected to said gating means for receiving said synchronizing pulses during said predetermined range of counts, and means connected to said second counting means for providing a signal indicative of the absence of an interlaced relationship when said second counting means attains a count less than a predetermined count during said predetermined range of counts.

Claim 26

Vertical synchronizing circuitry as defined in claim 22 wherein said means connected to said second counting means includes second gating means connected to said second counting means for providing an output signal when said second counting means attains a predetermined count, integrating means connected to said second gating means whereby said output signal from said second gating means discharges said integrating means, and switching means connected to said integrating means for providing a signal to modify the operation of said first-named counting means when said integrating means attains a predetermined charge.

Claim 27

Vertical synchronizing circuitry as defined in claim 17 wherein said first detecting means includes first gating means connected to said counting means and to said synchronizing pulse separator, integrating means connected to said first gating means whereby said first gating means discharges said integrating means when a vertical synchronizing pulse occurs during a predetermined range of counts of said counting means, and second gating means connected to said integrating means and to said synchronizing pulse separator for coupling a vertical synchronizing pulse to a reset input of said counting means when said integrating means attains a predetermined charge.