Synchronizing system

Claim 2

A synchronization system for providing an output signal in synchronism with synchronization signals subject to noise interference, said system comprising: generating means for producing signals of a frequency desired to be synchronized with said synchronization signals, first means coupled to said generating means for detecting a phase error between said signals and said synchronization signals, and second means for detecting signals whose duration is equal to said synchronization signal duration, said second means being coupled to said means for producing a signal representative of said phase error and enabled by said signal representative of said phase error only during an out-of-phase condition between said signals and said synchronization signals for producing a reset pulse in fixed time relationship to said synchronization signal, said reset pulse being coupled to said geNerating means for controlling said generating means to change the phase of said signals produced by said generating means to be in timed relationship with said synchronization signals whereby noise pulses of a duration less than said synchronization signal do not reset said generating means.

Claim 3

A circuit as defined in claim 1 wherein said generating means comprises an oscillator and a divider counter which divides the oscillator frequency to produce signals of the desired frequency, said divider counter being resetable to vary the phase of the output signal.

Claim 4

A circuit as defined in claim 2 wherein said oscillator is a multivibrator circuit.

Claim 5

A circuit as defined in claim 1 wherein said means for comparing the phase of said signals with said synchronization signals comprises: a coincidental gate, and control means for producing an enabling signal when said coincident gate detects a phase error between said synchronization signals and said internally generated signals.

Claim 6

A circuit as defined in claim 1 wherein said means for signals whose duration is equal to said synchronization signal comprises a pulse width detector to detect signals having a time duration of synchronization signals.

Claim 7

A circuit as defined in claim 5 wherein said pulse width detector includes gate circuit means for producing a reset pulse which is applied to said generating means to synchronize said signals produced by said generating means with said detected synchronization signal.

Claim 8

A synchronization system comprising: an oscillator synchronized by first synchronizing pulses to provide output signals frequency related by an integer multiple to said first synchronization pulse frequency, a frequency divider circuit coupled to said oscillator for converting said oscillator output signals into second frequency signals, a coincidence detector, means for applying said second frequency signals to said coincidence detector, a source of second synchronization signals, means for applying said second synchronization signals to said coincidence detector, said second synchronization signals having a frequency to which said second frequency signals are to be synchronized, said coincidence detector for detecting being selected phase differences between said second frequency signals and said second synchronizing signals equal to the period of said oscillator output signals, and pulse width detector means coupled to said coincidence detector and having said second synchronization signals applied thereto for detecting the presence of said second synchronization signals and for providing a reset signal in response to said second synchronization signals, said reset signal being applied to said frequency divider circuit to lock the phase of said second frequency signals produced thereby to said second synchronization signals when said coincidence detector detects phase disagreement between said second synchronization signals and said second frequency signals.

Claim 9

A synchronization system comprising: an oscillator synchronized by first synchronizing pulses to provide output signals frequency related by an integer multiple to said first synchronization pulse frequency, a frequency divider circuit coupled to said oscillator for converting said oscillator output signals into second frequency signals, a coincidence detector, means for applying said second frequency signals to said coincidence detector, a source of second synchronization signals, means for applying said second synchronization signals to said coincidence detector, said second synchronization signals having a frequency to which said second frequency signals are to be synchronized, said coincidence detector for detecting being selected phase differences between said second frequency signals and said second synchronizing signals equal to the period of said oscillator output signals, and pulse width detector means coupled to said coincidence detector and having said second synchronization signals applied thereto for detecting the presence of said second synchronization signals and for providing a reset signal in response to said second synchronization signals, said reset signal being applied to said frequency divider circuit to lock the phase of said second frequency signals produced thereby to said second synchronization signals when said coincidence detector detects phase disagreement between said second synchronization signals and said second frequency signals.

Claim 10

A circuit as defined in claim 7 wherein said pulse width detector produces said control signal only in response to an applied signal having a pulse width at least as long a time duration as said second synchronizing signals.

Claim 11

In a television receiver, a vertical deflection signal generator comprising: a clock pulse generator synchronized to twice the horizontal synchronization pulse frequency to produce clock pulses, resetable counter means coupled to said generator for producing vertical deflections frequency signals from said clock pulses, a coincidence detector circuit, means for applying vertical synchronization pulses to said coincidence detector, means for applying said vertical deflection frequency signals to said coincidence detector, said coincidence detector adapted to provide an enabling pulse in the event said vertical synchronization pulses are in phase disagreement with said vertical deflection signals, a pulse width detector coupled to sAid coincidence detector and activated by said enabling pulse from said coincidence detector, means for applying said clock pulses to said pulse width detector, means for applying said vertical synchronization signals to said pulse width detector, and gate circuit means coupled to said pulse width detector and to said divider counter and adapted to provide a reset pulse which is applied to said divider counter to reset said divider counter only when a predetermined number of clock pulses have been detected by said pulse width detector, thereby indicating the presence of a vertical synchronization pulse, said divider counter being responsive to said reset pulse to cause said vertical deflection frequency signals generated therein to be in synchronism with said vertical synchronization signals.

Claim 12

In a television receiver, a vertical deflection signal generator comprising: a clock pulse generator synchronized to twice the horizontal synchronization pulse frequency to produce clock pulses, resetable counter means coupled to said generator for producing vertical deflections frequency signals from said clock pulses, a coincidence detector circuit, means for applying vertical synchronization pulses to said coincidence detector, means for applying said vertical deflection frequency signals to said coincidence detector, said coincidence detector adapted to provide an enabling pulse in the event said vertical synchronization pulses are in phase disagreement with said vertical deflection signals, a pulse width detector coupled to sAid coincidence detector and activated by said enabling pulse from said coincidence detector, means for applying said clock pulses to said pulse width detector, means for applying said vertical synchronization signals to said pulse width detector, and gate circuit means coupled to said pulse width detector and to said divider counter and adapted to provide a reset pulse which is applied to said divider counter to reset said divider counter only when a predetermined number of clock pulses have been detected by said pulse width detector, thereby indicating the presence of a vertical synchronization pulse, said divider counter being responsive to said reset pulse to cause said vertical deflection frequency signals generated therein to be in synchronism with said vertical synchronization signals.

Claim 13

A circuit as defined in claim 9 wherein said pulse width detector further includes input gate means adapted to pass clock pulses upon the coincident arrival of said enabling pulses and said synchronization signals which are applied to said pulse width detector.

Claim 14

A circuit as defined in claim 10 wherein said clock pulses from said input gate means are applied to counter means.

Claim 15

A circuit as defined in claim 11 wherein said gate circuit means is coupled to said counter means and responsive to signals therefrom to produce a reset pulse only after a predetermined number of clock pulses have been passed by said input gate means.

Claim 16

In an image reproducing system of the type responsive to a video signal having recurrent horizontal and vertical synchronization pulses, a vertical synchronization system comprising: means for providing a signal source having a repetition rate related to the horizontal synchronization pulse repetition rate, a frequency divider coupled to said signal source to provide an output signal related in repetition rate and phase to said vertical synchronization pulse, said frequency divider being responsive to reset pulses to control the initiation of the frequency division and thereby the phase of the output signal from said frequency divider, vertical synchronization pulse detecting means coupled to receive said vertical synchronization pulses and a higher frequency signal for producing an output signal in response to the coincidence of a vertical synchronization pulse and a predetermined number of cycles of said higher frequency signal, coincidence detector means coupled to receive said output signal from said frequency divider and said vertical synchronization signal, and reset pulse developing means coupled to said vertical synchronization pulse detecting means and said coincidence detector to reset said frequency divider in the absence of proper coincidence between said output signal from said frequency divider and said vertical synchronization pulses and when said vertical synchronization detecting means provides an output pulse.

Claim 17

In an image reproducing system of the type responsive to a video signal having recurrent horizontal and vertical synchronization pulses, a vertical synchronization system comprising: means for providing a signal source having a repetition rate related to the horizontal synchronization pulse repetition rate, a frequency divider coupled to said signal source to provide an output signal related in repetition rate and phase to said vertical synchronization pulse, said frequency divider being responsive to reset pulses to control the initiation of the frequency division and thereby the phase of the output signal from said frequency divider, vertical synchronization pulse detecting means coupled to receive said vertical synchronization pulses and a higher frequency signal for producing an output signal in response to the coincidence of a vertical synchronization pulse and a predetermined number of cycles of said higher frequency signal, coincidence detector means coupled to receive said output signal from said frequency divider and said vertical synchronization signal, and reset pulse developing means coupled to said vertical synchronization pulse detecting means and said coincidence detector to reset said frequency divider in the absence of proper coincidence between said output signal from said frequency divider and said vertical synchronization pulses and when said vertical synchronization detecting means provides an output pulse.